SPRZ452I july 2018 – may 2023 AM6526 , AM6528 , AM6546 , AM6548
DDR: Mode Register write busy indicator not cleared after completing software-driven mode register access
If the hardware-driven mode register access (automatic DDR4 Mode-Register-Set or periodic LPDDR4 Mode-Register-Read for temperature derating) starts just before sending software-driven mode register access (setting the MRCTRL0.mr_wr register to 1), the MRSTAT.mr_wr_busy field is not cleared to 0 until the next hardware-driven mode-register access starts.
Avoid conflict between software-driven and hardware-driven mode register accesses. For DDR4, disable the sources of hardware-driven mode register accesses by writing the following registers before initiating the software-driven mode register access.
PWRCTL.mpsm_en = 0
PWRCTL.selfref_sw = 0
PWRCTL.selfref_en = 0
HWLPCTL.hw_lp_en = 0
DFIPHYMSTR.dfi_phymstr_en = 0
For LPDDR4, disable the temperature derating feature (set register DERATEEN.derate_enable to 0) before initiating the software-driven MR access.