SPRZ455D december 2020 – june 2023 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
ADVANCE INFORMATION
DDR: VRCG High Current Mode Must be Used During LPDDR4
CBT
The DDR PHY updates VREFca for the command/address bus during LPDDR4 Command Bus Training (CBT). Bit 3 in LPDDR4 Mode Register 13 (MR13) defines the VRef Current Generator (VRCG) mode inside the LPDDR4 device. If this bit is set to 0, the VREFca settling time is too long for subsequent operations to work properly. To ensure proper operation of CBT, bit 3 in MR13 must be set to 1 (VRef Fast Response high current mode) during CBT.
Set the following fields to 1 before enabling CBT, and clear to 0 after CBT is complete.
For chip select 0: PI_MR13_DATA_0[3] in the DDRSS_PI_259 register.
For chip select 1: PI_MR13_DATA_1[3] in the DDRSS_PI_261 register.