SPRZ457I January 2021 – December 2024 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Boot: GPMC NAND configured to slower clock speed
When using GPMC NAND boot mode the GPMCFCLKDIVIDER field of the GPMC_CONFIG1 register bit [1:0] (i.e. GPMCFCLKDIVIDER) gets set to 1 which causes a divide by 2 for the GPMC_FCLK.
The ROM uses very conservative CONFIG timing values anyways so end result may not really adversely affect throughput.
None.