SPRZ458F May 2019 – February 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
This document describes the known exceptions to the functional specifications (advisories). This document may also contain usage notes. Usage notes describe situations where the device's behavior may not match presumed or documented behavior. This may include behaviors that affect device performance or functional correctness.
NUMBER | TITLE | SILICON REVISIONS AFFECTED | |
---|---|---|---|
0 | A | ||
Section 3.1.1 | PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear | Yes | Yes |
Section 3.1.2 | Caution While Using Nested Interrupts | Yes | Yes |
Section 3.1.3 | GPIO: GPIO Data Register is Reset by CPU1 Reset Only | Yes | Yes |
Section 3.1.4 | McBSP: XRDY bit can Hold the Not-Ready-Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY bit is in its Ready State (1) | Yes | Yes |
Section 3.1.5 | Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature | Yes | Yes |