SPRZ458F May   2019  – February 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   TMS320F2838x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 GPIO: GPIO Data Register is Reset by CPU1 Reset Only
      4. 3.1.4 McBSP: XRDY bit can Hold the Not-Ready-Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY bit is in its Ready State (1)
      5. 3.1.5 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4. 3.2.1 Advisory
      5. 3.2.2 Advisory
      6. 3.2.3 Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
  6. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

Advisory

HWBIST: RTOSINT Interrupt Asserted During HWBIST Run Does Not Get Logged

Revisions Affected

0, A

Details

During HWBIST, all valid interrupt sources except ERAD are logged. The application can read the ERAD System Event Interrupt status flags after HWBIST completion to check for any pending interrupts. This check is necessary only if the application uses ERAD functionalities.

Workaround

When RTOSINT from ERAD is enabled, the interrupt generated during HWBIST execution will not be latched inside the CPU. The application should perform the following sequence of operations (before/after HWBIST execution) so RTOSINT information is not lost.

  1. Disable RTOSINT:
    • Set ERAD_COUNTER_REGS.CTM_CNTL.RTOSINT = 0 if the Counter module is configured to generate RTOSINT or
    • Set ERAD_COUNTER_REGS.HWBP_CNTL.RTOSINT = 0 if the HWBP module is configured to generate RTOSINT
  2. HWBIST context save
  3. HWBIST execution
  4. HWBIST context restore
  5. Check the STATUS registers for any ERAD events that occurred during HWBIST execution and take the appropriate action:
    • Set ERAD_COUNTER_REGS.CTM_STATUS.EVENT_FIRED = 1 to check for any CTM events or
    • Set ERAD_COUNTER_REGS.HWBP_STATUS.EVENT_FIRED = 1 to check for any HWBP events
  6. Enable RTOSINT:
    • Set ERAD_COUNTER_REGS.CTM_CNTL.RTOSINT = 1 if the Counter module is configured to generate RTOSINT or
    • Set ERAD_COUNTER_REGS.HWBP_CNTL.RTOSINT = 1 if the HWBP module is configured to generate RTOSINT