SPRZ458F May   2019  – February 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   TMS320F2838x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 GPIO: GPIO Data Register is Reset by CPU1 Reset Only
      4. 3.1.4 McBSP: XRDY bit can Hold the Not-Ready-Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY bit is in its Ready State (1)
      5. 3.1.5 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4. 3.2.1 Advisory
      5. 3.2.2 Advisory
      6. 3.2.3 Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
  6. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

1.2 Advisories Matrix

Table 1-2 Advisories Matrix
MODULE DESCRIPTION SILICON REVISIONS AFFECTED
0 A
ADC ADC: External SOC Trigger (ADCEXTSOC) Cannot be Used to Trigger Multiple ADCs Yes No
ADC ADC: DMA Read of Stale Result Yes Yes
ADC ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes Yes
DCAN During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer Yes Yes
MCAN Message Order Inversion When Transmitting From Dedicated Tx Buffers Configured With Same Message ID Yes Yes
EMAC EMAC: Additional Words in Reception Buffer Yes Yes
EMAC EMAC: Packet Filtering With TCP/UDP Filter (DNTU bit) Does not Work as Intended Yes Yes
ePWM ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window Yes Yes
ePWM ePWM: Trip Events Will Not be Filtered by the Blanking Window for the First 3 Cycles After the Start of a Blanking Window Yes Yes
ePWM ePWM: Event Latch (DCxEVTxLAT) of "DC Event-Based CBC Trip" May not Extend Trigger Pulse as Expected When Asynchronous Path is Selected Yes No
ESC ESC: EtherCAT Slave Controller Distributed Clocking (DC) Mode is not Supported Yes No
ESC ESC: EtherCAT Slave Controller may not Work with a Non-Gigabit PHY Yes No
ESC ESC: The CPU1 DMA Access is Only Available to the Lower 4KB of the ESC RAM Memory Map Yes No
Ethernet Ethernet: MAC Receive VLAN Tag Hash Filter Always Operates in Default Mode Yes Yes
Ethernet Ethernet: Assertion of Wrong Early Transmit Interrupt (ETI) for Context Descriptor Yes Yes
Ethernet Ethernet: Incorrect Flexible Pulse-per-Second (PPS) Output Interval When Fine Correction Method is Used Yes No
Ethernet Ethernet: False Dribble and CRC Error Reported in RMII 10Mbps Mode for a Specific Phase Relation Between MAC Receiver Clock and Assertion of RMII CRS_DV Input Yes No
FPU FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation Yes Yes
FSI FSI: RX FIFO Spurious Overrun Yes No
GPIO GPIO: Open-Drain Configuration may Drive a Short High Pulse Yes Yes
HWBIST HWBIST: Avoiding Spurious Interrupts While Using HWBIST Yes Yes
HWBIST HWBIST: No Cross-Triggering From One CPU While One of the C28x Cores is Going Through HWBIST Check Yes Yes
HWBIST HWBIST: RTOSINT Interrupt Asserted During HWBIST Run Is Not Logged Yes Yes
I2C I2C: Target Transmitter Mode, Standard Mode SDA Timings Limitation Yes Yes
INTOSC INTOSC: VDDOSC Powered Without VDD can Cause INTOSC Frequency Drift Yes No
MCD MCD: Missing Clock Detect Should be Disabled When the PLL is Enabled (PLLCLKEN = 1) Yes Yes
Memory Memory: Prefetching Beyond Valid Memory Yes Yes
MPOST MPOST: Memory Power-on-Self-Test will not Work at Full Speed Yes No
Reset Reset: Elevated VDD Current During Reset Yes No
SDFM SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR Settings Will Trigger Spurious Comparator Events Yes Yes
SDFM SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR) Will Trigger Spurious Data Acknowledge Events Yes Yes
SDFM SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events Yes Yes
SYSTEM SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang Yes Yes
USB USB: USB DMA Event Triggers are not Supported Yes Yes
Watchdog Watchdog: WDKEY Register is not EALLOW-Protected Yes Yes