SPRZ458F May   2019  – February 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   TMS320F2838x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 GPIO: GPIO Data Register is Reset by CPU1 Reset Only
      4. 3.1.4 McBSP: XRDY bit can Hold the Not-Ready-Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY bit is in its Ready State (1)
      5. 3.1.5 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4. 3.2.1 Advisory
      5. 3.2.2 Advisory
      6. 3.2.3 Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
  6. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

Advisory

I2C: Target Transmitter Mode, Standard Mode SDA Timings Limitation

Revision Affected

0, A

Details

The I2C peripheral present on the MCU is a Fast-mode device; it will clock-stretch the SCL (Clock) line when used with a Standard-mode host.

There is a requirement from the I2C Specification for a Fast-mode device used in a Standard-mode system to meet tSU:DAT (data set-up time) + tr(max) (rise time) before releasing the SCL line. See Footnote 4 of the "Characteristics of the SDA and SCL bus lines for Standard, Fast, and Fast-mode Plus I2C-bus devices" table in the NXP Semiconductors I2C-bus specification and user manual (UM10204).

However, the C2000 I2C clock-stretches the SCL line by a fixed amount = 6 * fmod Clock (I2C Clock rate of the C2000) in the above scenario. When the C2000™ microcontroller is acting as a target transmitter with a Standard-mode host, it is possible for the clock line (SCL) to be released by the C2000 before the data (SDA) is ready, if the tr of SDA is too long.

The "Pull-up resistor sizing" section in the NXP Semiconductors I2C-bus specification and user manual (UM10204) gives more details on choosing the appropriate PU resistor (Rp), based on the rise time (tr) and bus capacitance (Cb) shown in Equation 1.

Equation 1. Rp(max)=tr0.8473×Cb

Workaround

  1. Reducing tr with a strong pullup
    In order to ensure that tSU:DAT + tr(max) is met, the user can configure the pullup resistance on the SDA line such that it meets the constraints listed in the SDA Data Rise Time Requirement column of Table 3-1 based on the value of fmod Clock in their system. This will ensure that the data present on the SDA line is valid when the C2000 releases the SCL signal. Table 3-2 gives suggested Rp resistor values for a given fmod Clock (MHz) and Cb (bus capacitance). For other values of Cb, please use Equation 1 to calculate the value of Rp needed in the system.
    Table 3-1 Data Rise Time Requirements for C2000 as Target Transmitter with Standard-Mode Host
    fmod Clock (MHz) fmod Period (ns) SCL Clock- Stretch Delay from C2000 I2C (ns): (6*fmod Clock) Data Set-up Time (ns): tSU:DAT (Standard Mode) SDA Data Rise Time Requirement (ns): tr
    7 142.9 857 250 607
    8 125 750 500
    9 111 666 416
    10 100 600 350
    11 90.9 545 295
    12 83.3 500 250
    Table 3-2 Pullup Resistor (Rp) Values for Common Bus Capacitances (Cb)
    fmod Clock (MHz) SDA Data Rise Time Requirement (ns): tr Rp (kΩ) for
    Cb = 100 pF    		 Rp (kΩ) for
    Cb = 200 pF    		 Rp (kΩ) for
    Cb = 300 pF    		 Rp (kΩ) for
    Cb = 400 pF
    7 607 7.1 3.5 2.3 1.7
    8 500 5.9 2.9 1.9 1.4
    9 416 4.9 2.4 1.6 1.2
    10 350 4.1 2.0 1.3 1.0
    11 295 3.4 1.7 1.1 0.8
    12 250 2.9 1.4 0.9 0.7
  2. tr = 1000 ns
    This workaround is not preferred due to restrictions in general I2C usage, use Workaround 1 when possible.
    If the system is such that it requires 1000 ns of rise time on the SDA line, the C2000 I2C fmod Clock can be configured to 4.8 MHz so the clock-stretching (6 * fmod Clock) satisfies this requirement. This results in tr = (1/4.8 MHz) * 6 = 1000 ns. This workaround is only valid in systems where the C2000 I2C is the target on the I2C bus. Note that 4.8 MHz is outside the data sheet's required range of 7 MHz to 12 MHz for fmod Clock. Using fmod at 4.8 MHz, even though it is outside of the data sheet's required range, will work for the C2000 I2C in Target mode on a Standard-mode host bus. Using fmod = 4.8 MHz in any other configurations except the one listed in this workaround will cause other timing parameters to be violated and is not allowed.