SPRZ466C March   2020  – February 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   1
  2.   TMS320F28002x Real-Time MCUs Silicon ErrataSilicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3. 3.2.1 Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7. 3.2.2 Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11. 3.2.3 Advisory
      12.      Advisory
      13. 3.2.4 Advisory
      14.      Advisory
      15. 3.2.5 Advisory
      16. 3.2.6 Advisory
  6. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1.      Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

3.2.5 Advisory

Avoiding Spurious Interrupts While Using HWBIST

Revisions Affected

0, A

Details

HWBIST has the capability to log interrupts that are received while the CPU is under test and re-issue them after HWBIST completes. Interrupts that are received in the clock cycle before the interrupt logging is enabled will be executed before the HWBIST runs. In the next cycle, once interrupt logging is enabled, interrupts will be logged and re-issued once the HWBIST completes.

The interrupt events for CPU Timer 1 and CPU Timer 2 are valid for 2 SYSCLK cycles. If the first cycle happens a cycle before interrupt logging is enabled and the second cycle coincides with the enabling of interrupt logging, the interrupt will be executed once before the logging (clearing the CPU Timer TCR.TIF flag), but then will be logged by the interrupt logger and triggered again after HWBIST completes. Since the TCR.TIF flag was already cleared by the previous ISR, this is an unexpected spurious interrupt.

Note that this scenario is only applicable to the non-PIE CPU Timer interrupts. The CPU Timer 0 interrupt is managed by the PIE and its pulse width is only one SYSCLK cycle.

Workaround

Disable CPU Timer 1 and 2 interrupts before enabling interrupt logging and restore them later. This workaround is already implemented in the C2000 Software Diagnostic Library in the stl_hwbist_s.asm file. The steps are:

  1. Clear the timer interrupt enable bit TCR.TIE for CPU Timers 1 and 2.
  2. Run normal HWBIST sequence: save registers, enable interrupt logging, run HWBIST, restore registers, end interrupt logging.
  3. Check if the CPU Timers' TCR.TIF flags are set. If the flags are set, set the corresponding CPU IFR bit to trigger the interrupt.
  4. Restore TCR.TIE.