SPRZ491D december 2020 – june 2023 DRA821U , DRA821U-Q1
PCIe: Link up failure when unused lanes are not assigned to PCIe Controller
PCIe fails to link up if SERDES lanes not used by PCIe are assigned to another protocol. For example, link training fails if lanes 2 and 3 are assigned to another protocol while lanes 0 and 1 are used for PCIe to form a two lane link. This failure is due to an incorrect tie-off on an internal status signal indicating electrical idle.
Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, PCIe sees unused lanes to be out of electrical idle and this causes LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to occur. If a receiver is not detected on the first receiver detection attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and again moves forward to Detect.Active state without waiting for 12ms as required by PCIe base specification. Since wait time in Detect.Quiet is skipped, multiple receiver detect operations are performed back-to-back without allowing time for capacitances on the transmit lines to discharge. This causes subsequent receiver detections to always fail even if a receiver gets connected eventually.
Enable 2ms minimum wait time for Detect.Quiet state using DQMDC field in PCIE_CORE_LM_I_PL_CONFIG_2_REG register. This will cause LTSSM to wait for a minimum of 2ms in Detect.Quiet state. This allows sufficient time for capacitances on transmit lines to discharge between successive receiver detect operation.