SPRZ491D december 2020 – june 2023 DRA821U , DRA821U-Q1
PCIe: SerDes Reference Clock Output does not comply to Vcross, Rise-Fall Matching, and Edge Rate limits
The PCIe Reference Clock Output of the SerDes does not comply with the PCI-SIG specifications for VCROSS and Edge Rate limits. Therefore, some external PCIe components may have an issue receiving and using the Reference Clock. However, the SerDes in this Device family does not have an issue accepting this non-compliant Reference Clock. This means that a link that connects the SerDes in one Device to the SerDes in a second Device will not have an issue when one Device generates the Reference Clock and the other Device receives the Reference Clock.
Option 1:
Add an external circuit to the PCIe Reference Clock SERDES0_REFCLK_P/N Output to bring the signal into electrical compliance.
A passive re-biasing circuit can be used to achieve a compliant Vcross level:
There are two options to achieve a compliant Edge Rate:
Option 2:
Use an external clock source to supply the PCIe Reference Clock to both the Root Complex and End Point Devices of the Link.