SPRZ491D december 2020 – june 2023 DRA821U , DRA821U-Q1
Compute Cluster: A72 Corepac unable to be powered down
If A72 Corepac powerdown is requested by software when DebugSS LPSC is OFF, Powerdown handshake could hang. When DebugSS LPSC is OFF, Clock to MSMC wrap's Debug block is gated and depending on initial state of A72 related debug components in this debug block, A72's LPSC may never receive disable_ack.
Before Initiating A72 Corepac Powerdown sequence software needs to make sure DebugSS LPSC is ON. This enables clock to MSMC wrap Debug block and ensures A72 Powerdown Handshake completes.