SPRZ496D October   2021  – May 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision 0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 0 Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision 0 Advisories
      1. 3.2.1  Advisory
      2.      Advisory
      3.      Advisory
      4. 3.2.2  Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9. 3.2.3  Advisory
      10.      Advisory
      11. 3.2.4  Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15. 3.2.5  Advisory
      16.      Advisory
      17. 3.2.6  Advisory
      18. 3.2.7  Advisory
      19.      Advisory
      20. 3.2.8  Advisory
      21.      Advisory
      22. 3.2.9  Advisory
      23. 3.2.10 Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
  6. 4Documentation Support
  7. 5Trademarks
  8. 6Revision History

Advisory

BOR: VDDIO Between 2.45 V and 3.0 V can Result in Multiple XRSn Pulses

Revision Affected

0

Details

The BOR can generate repeating XRSn assertions and deassertions when the VDDIO supply voltage is between 2.45 V and 3.0 V. It is recommended that the XRSn pin not be used directly as a reset to any other devices in the system.

The F28003x BOR is effective for internally holding the device in a known reset state, even when these XRSn pulses are occurring. The device will not branch to application code or bootloaders, and all other pins will be held in their reset state until the VDDIO supply rises above 3.0 V.

Workarounds

  1. Ignore the extra XRSn transitions during power up, power down, and BOR events. The extra XRSn pulses will have no effect on the F28003x device operation itself.
  2. If XRSn pulses would cause undesired system behavior with other system components, then do not use XRSn to drive other devices. An external voltage supervisor can be used for these applications.
  3. For applications that need to avoid these pulses during normal power up and power down:
    1. Power up: Follow the SRSUPPLY requirement in the Recommended Operating Conditions table of the TMS320F28003x Real-Time Microcontrollers data sheet; no extra XRSn low pulses will occur.
    2. Power Down: To avoid any deassertion of XRSn during power down, design the power supply so that VDDIO passes through the range from 3.0 V to 2.45 V within 25 µs. If some voltage rise on XRSn is acceptable, then the time constant of the RC circuit implemented on XRSn can be calculated to ensure the voltage does not rise above a system-specified threshold.