Revisions Affected

0, A, B, C

Details

If ADCINTSELxNx[INTxCONT] = 0, then interrupts will stop when the ADCINTFLG is set and no additional ADC interrupts will occur.

When an ADC interrupt occurs simultaneously with a software write of the ADCINTFLGCLR register, the ADCINTFLG will unexpectedly remain set, blocking future ADC interrupts.

Workarounds

1. Use Continue-to-Interrupt Mode to prevent the ADCINTFLG from blocking additional ADC interrupts:

   
   ADCINTSEL1N2[INT1CONT] = 1;
   ADCINTSEL1N2[INT2CONT] = 1;
   ADCINTSEL3N4[INT3CONT] = 1;
   ADCINTSEL3N4[INT4CONT] = 1;
   

2. Ensure there is always sufficient time to service the ADC ISR and clear the ADCINTFLG before the next ADC interrupt occurs to avoid this condition.
3. Check for an overflow condition in the ISR when clearing the ADCINTFLG. Check ADCINTOVF immediately after writing to ADCINTFLGCLR; if it is set, then write ADCINTFLGCLR a second time to ensure the ADCINTFLG is cleared. The ADCINTOVF register will be set, indicating an ADC conversion interrupt was lost.

   
   AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;        //clear INT1 flag
   if(1 == AdcaRegs.ADCINTOVF.bit.ADCINT1)       //ADCINT overflow
   {
       AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;    //clear INT1 again
   // If the ADCINTOVF condition will be ignored by the application
   // then clear the flag here by writing 1 to ADCINTOVFCLR.  
   // If there is a ADCINTOVF handling routine, then either insert 
   // that code and clear the ADCINTOVF flag here or do not clear 
   // the ADCINTOVF here so the external routine will detect the 
   // condition.
   //    AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1;  // clear OVF
   }