SPRZ506D October   2022  – December 2024 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision C Usage Notes and Advisories
    1. 3.1 Silicon Revision C Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision C Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8. 3.2.1 Advisory
      9.      Advisory
      10. 3.2.2 Advisory
      11. 3.2.3 Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16. 3.2.4 Advisory
      17.      Advisory
      18. 3.2.5 Advisory
      19.      Advisory
  6. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
  7. 5Silicon Revision A Usage Notes and Advisories
    1. 5.1 Silicon Revision A Usage Notes
    2. 5.2 Silicon Revision A Advisories
  8. 6Silicon Revision 0 Usage Notes and Advisories
    1. 6.1 Silicon Revision 0 Usage Notes
    2. 6.2 Silicon Revision 0 Advisories
  9. 7Documentation Support
  10. 8Trademarks
  11. 9Revision History

Advisory

GPIO19/X1: Application of Voltage Outside Recommended Operating Conditions can Cause Device Misbehavior

Revisions Affected

0, A, B, C

Details

If a voltage in excess of the recommended operating conditions (above VDDIO or below VSS) is applied to the GPIO19/X1 pin, the device may not operate correctly. Effects can include:

  • Device not exiting the boot ROM after power up and/or XRSn deassertion
  • Device is unable to connect through JTAG
  • Impact to the device clock frequency during application code execution

Workaround

Pay special attention to the layout and routing of the GPIO19/X1 pin on this device. While an out-of-specification voltage on this pin is the cause of the issue; the source of the excess voltage may come from the external components connected to the pin, or from noise-coupling from other sources on the PCB. If a single-ended clock is applied to GPIO19, overvoltage can also arise from impedance mismatching of the external clock driver and the characteristics of this pin. Verification of signal integrity is recommended to determine if the applied voltage is within the data sheet tolerance.

If this pin is unused in the system, the recommendations for unused pins from the data sheet still apply:

  • No connection (input mode with internal pullup enabled)
  • No connection (output mode with internal pullup disabled)
  • Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)

However, if the PCB design allows for it, a modification of the final bullet is preferred to minimize the impact of noise on this pin:

  • Tie this pin directly to VSS