SPRZ507D January   2023  – November 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7. 3.2.1 Advisory
      8.      Advisory
      9. 3.2.2 Advisory
      10.      Advisory
      11. 3.2.3 Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15. 3.2.4 Advisory
      16. 3.2.5 Advisory
      17.      Advisory
      18.      Advisory
      19. 3.2.6 Advisory
      20.      Advisory
  6. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
    2. 4.2 Silicon Revision A Advisories
      1. 4.2.1 Advisory
  7. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
  8. 6Documentation Support
  9. 7Trademarks
  10. 8Revision History

4.2.1 Advisory

MPOST: Execution of Memory Power-On Self-Test will not Execute on Some Early Material

Revisions Affected

0, A

Details

MPOST (Memory Power-On Self-Test) can be used in functional-safety applications to test the device memory on power up. This feature is activated by writing to the Z1_GPREG2.MPOST bits using the DCSM Security tool. On impacted material, MPOST will not execute even if the Z1_GPREG2.MPOST bits are written to.

Workaround

  • Check OTP Revision: Fixed material will have an OTP revision number greater than 1. The OTP revision number can be determined using Table 4-1. MPOST will work as documented in the TMS320F280015x Real-Time Microcontrollers Technical Reference Manual.
  • Equivalent memory test in F280015x SDL: Using the STA_MARCH function that is included as part of the F280015x Software Diagnostic Library (SDL) is an equivalent test of the memories that can be executed from the main application. The SDL is included in the C2000Ware installation in the following parent directory: C:/ti/c2000/C2000Ware_5_02_00_00/libraries/diagnostic/f280015x/. See the "test application" project in the "examples" folder as well as the description of the STL in the "docs" subfolder on how to invoke this memory check.
Table 4-1 OTP Revision Number Location
ADDRESS 8-bit MSB 8-bit LSB
0x0007 11DE 0x5A OTP revision