SPRZ507D January   2023  – November 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7. 3.2.1 Advisory
      8.      Advisory
      9. 3.2.2 Advisory
      10.      Advisory
      11. 3.2.3 Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15. 3.2.4 Advisory
      16. 3.2.5 Advisory
      17.      Advisory
      18.      Advisory
      19. 3.2.6 Advisory
      20.      Advisory
  6. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
    2. 4.2 Silicon Revision A Advisories
      1. 4.2.1 Advisory
  7. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
  8. 6Documentation Support
  9. 7Trademarks
  10. 8Revision History

3.2.3 Advisory

Flash: Single-Bit ECC Error Interrupt is Not Generated

Revisions Affected

0, A, B

Details

If the single-bit ECC error threshold is configured as 0, the single-bit error interrupt is not generated when there is a single-bit error.

Workaround

Set the error threshold bit field (FLASH_ECC_REGS ERR_THRESHOLD.ERR_THRESHOLD field) to a value greater than or equal to 1. Note that the default value of the threshold bit field is 0.