SPRZ530C April   2022  – July 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0 Usage Notes
      1.      i2134
    2. 3.2 Silicon Revision 1.0 Advisories
      1.      i2049
      2.      i2062
      3.      i2063
      4.      i2064
      5.      i2065
      6.      i2079
      7.      i2091
      8.      i2097
      9.      i2103
      10.      i2120
      11.      i2134
      12.      i2137
      13.      i2146
      14.      i2157
      15.      i2159
      16.      i2160
      17.      i2161
      18.      i2163
      19.      i2166
      20.      i2177
      21.      i2189
      22.      i2190
      23.      i2196
      24.      i2197
      25.      i2205
      26.      i2215
      27.      i2216
      28.      i2219
      29.      i2232
      30.      i2234
      31.      i2235
      32.      i2237
      33.      i2242
      34.      i2243
      35.      i2244
      36.      i2249
      37.      i2253
      38.      i2271
      39.      i2272
      40.      i2278
      41.      i2279
      42.      i2283
      43.      i2307
      44.      i2308
      45.      i2310
      46.      i2311
      47.      i2312
      48.      i2313
      49.      i2316
      50.      i2320
      51.      i2326
      52.      i2329
      53.      i2351
      54.      i2362
      55.      i2366
      56.      i2371
      57.      i2372
      58.      i2378
      59.      i2381
      60.      i2383
      61.      i2399
      62.      i2401
      63.      i2409
      64.      i2414
      65.      i2419
      66.      i2422
      67.      i2435
      68.      i2437
  5.   Trademarks
  6.   Revision History

i2065


C71x: The C71x Memory System and CPU May Stall Indefinitely in the Presence L1D Snoops

Details:

These are transactions and conditions that need to happen in a small time window.

Transactions:

  1. Streaming engine reads to MSMC or DDR, which miss L2 cache, and go out as a read to MSMC for a line fill.
  2. Streaming engine reads to MSMC or DDR, which miss L2 cache, but may be cached in L1D. These reads generate snoops to L1D.
  3. CPU loads miss L1D and L1D sends them to L2 for cache line fills (multiple reads).
  4. CPU loads or stores cause L1D to evict lines from its cache, resulting in victims to L2 (multiple victims).
  5. L1D is responding to snoops, with snoop data.
  6. MSMC is responding to the L2 misses with read response data.
  7. Snoop responses from L1D (#5) and read response from MSMC (#6) are being routed to streaming engine.

Conditions/Stalls:

  1. The L1D victims and snoop responses fill up the entire L1D pipeline and the buffers in L1D and L2, with the result that L1D is unable to send down any more victims or snoop responses to L2.
  2. L2 is processing the read misses from L1D, but is unable to send back any more read response data to L1D since the L1D pipeline is full.

In this situation, the memory system stops servicing streaming engine reads. This can cause the CPU to stall indefinitely.

Workaround(s):

There are multiple ways in which this can be avoided. Removing any one transaction prevents this stall from happening. Any of these workarounds can be used. They are independent of each other, and applying even one workaround will avoid this condition.

Workaround 1: Flush the buffer from the L1D cache, before reading from the streaming engine, which eliminates L1D snoops.

Workaround 2: Prevents L1D snoops by not sharing buffers between L1D and Streaming engine.

Workaround 3: Flush the L1D victim cache to prevent L1D victims.

Workaround 4: Map either the streaming engine reads or the CPU loads to L2, instead of MSMC or DDR, thus avoiding cache misses.