SPRZ569 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   TMS320F2838x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision 0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 0 Usage Notes
    2. 3.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3. 3.2.1 Advisory
      4.      Advisory
      5. 3.2.2 Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11. 3.2.3 Advisory
      12. 3.2.4 Advisory
      13. 3.2.5 Advisory
      14. 3.2.6 Advisory
  6. 4Documentation Support
  7. 5Trademarks
  8. 6Revision History

3.2.5 Advisory

System: Pending Misaligned Reads in the Pipeline After CPU Goes to Fault State Preventing NMI Vector Fetch

Revisions Affected

0

Details

The NMI handler fails to execute when three or more back-to-back C29 CPU faults caused by misaligned reads occur. When more than two faults are in the CPU pipeline, the CPU does not fetch the NMI vector as expected.

Workaround

Use ERAD-SEC counter:

  1. Choose ESM_GEN_EVENT as input to EPWMXBAR.
  2. Configure the ERAD-SEC1 counter in start-stop mode: start event as EPWMXBAR event, stop event as SEC1 event itself. This counter will be counting SYSCLK cycles.
  3. Configure the ERAD-SEC reference register to generate a match event and trigger an NMI (INT_EN and NMI_EN bits in SEC_CNTL register) on a count of 50.
  4. Configure ESM CPU1 to generate an NMI on the ERAD_CPU1_NMI event.