SWAU132 April 2024
The BP-CC3351 was designed with 2 JTAG headers (J10, J11) for SWD interface with the XDS110 debug probe. The signal assignment for these headers are described in the figures and tables below.
The main JTAG interface for the BP-CC3351 is via the LP-XDS110 (ET) that is connected to the 20pin header (J11). A XDS110 debug probe can also interface with this board via a 10-pin header (J10), however this header is not populated with the default kit.
Pin | Signal Name | Description |
---|---|---|
J10.1 | VCC_BRD_1V8 | 1.8V supply for reference voltage to connector |
J10.2 | SWDIO | Serial wire data in/out |
J10.4 | SWCLK | Serial wire clock |
J10.10 | RESET_1V8 | nReset (Enable line for CC3351) |
J10.3, J10.5, J10.7, J10.9 | GND | Board ground |
Pin | Signal Name | Description |
---|---|---|
J11.6 | SWCLK | Serial wire clock |
J11.8 | SWDIO | Serial wire data in/out |
J11.10 | RESET_1V8 | nReset (Enable line for the CC3351) |
J11.12 | UART_TX_1V8 | The CC3351 UART TX to host for BLE host controller interface |
J11.14 | UART_RX_1V8 | The CC3351 UART RX from host for BLE host controller interface |
J11.16 | VCC_BRD_1V8 | 1.8V supply for reference voltage to connector |
J11.18 | VCC_BRD_5V | 5V supply to BP-CC3351 from LP-XDS110 |
J11.1, J11.7, J11.13, J11.19, J11.20 | GND | Board ground |