SWAU133 July   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Overview
    2. 2.2 Setup
    3. 2.3 Header Information
  7. 3Software
    1. 3.1 Software Description
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
    1. 5.1 Compliance and Certifications
  10. 6Additional Information
    1. 6.1 Trademarks

2.1 Overview

The figures below show the features on the top and bottom side of the M2-CC3351 board, and some of the highlighted features are described below.

M2-CC3351 M2-CC3351 Features Figure 2-1 M2-CC3351 Features
  • The mounted 0 Ohm resistor can be swapped to a different position to do conducted testing with the connector on board (J1/J2); the default configuration allows use of the onboard chip antenna (refer to Figure 3-1). Alternatively, there is footprint for an SMA connector (J2) onboard to replace the onboard UF.L connector (J1) for performing conducted testing measurements with a compatible coaxial cable (refer to Figure 3-2).
  • There is an optional placement for a 32.768kHz oscillator (Y2), but the CC3351 already has an internal Slow Clock. The only tradeoff of not having the oscillator (Y2) is a higher power consumption when connected to an access point.
  • With the optional 2 pin header (J3), users can access or provide the 3.3v power source and the ground of the board.
  • The M2-CC3351 Gold finger Edge connector (J5) follows the PCIe M.2 form factor Type 2230 Key E, as such the board can be compatible with any host that has a 75-position host interface connector for type key E. Refer to Section 2.3 for more information on the pin out.
M2-CC3351 M2-CC3351 More Features Figure 2-2 M2-CC3351 More Features
  • The onboard LDO (U2) is used to derive 1.8V from the provided 3.3V.
  • There is an onboard Level Shifter (U3) for the device to receive only 1.8V for the nRESET Net signal .
  • An important note is that the Dual Inverter Buffer with Open-Drain Output (U4) allows the device to output the interrupt lines (Active Low) and conform to the PCI Express M.2 Specification. Since the component is open-drain, the host platform must have a 10K pull up; pads have been provided to add the resistor (R11 for IRQ_WL, and R12 for IRQ_BLE) in case that is not true.
  • There are resistors to optionally change the pin used for the HOST_nRESET and IRQ_WL_toHost net signals (refer to Section 2.3).