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Data Sheet
TPS650864 Configurable
Multirail PMU for Xilinx MPSoCs and FPGAs
1 Features
- Wide VIN range from 5.6V to 21V
- Three variable-output voltage synchronous
step-down controllers with D-CAP2™ Topology
- Scalable output current
using external fets with selectable current limit
- I2C DVS control from 0.41V to
1.67V in
10mV steps or 1V to 3.575V in
25mV steps
- Three variable-output voltage synchronous
step-down converters with dcs-control topology
- VIN range from
3V to 5.5V
- Up to 3 A of output
current
- I2C DVS control from 0.41V to
1.67V in
10mV steps or 0.425V to 3.575V
in 25mV steps
- Three LDO regulators with adjustable output
voltage
- LDOA1:
I2C-selectable voltage from 1.35V to 3.3V for up to 200mA of
output current
- LDOA2 and LDOA3:
I2C-selectable voltage from 0.7V to 1.5V for up to 600mA
of output current each
- VTT LDO for DDR memory termination
- Three load switches with slew rate control
- Up to 300mA of output
current with voltage drop less than 1.5% of nominal input voltage
- RDSON <
96mΩ at input voltage of 1.8V
- 5V fixed-output voltage LDO (LDO5)
- Power supply for gate
drivers of SMPS and for LDOA1
- Automatic switch to
external 5V buck for higher efficiency
- Built-in flexibility and configurability by factory OTP programming
- Six GPI pins configurable
to enable (CTL1 to CTL6) or sleep mode entry (CTL3 and CTL6) of any
selected rails
- Four GPO pins
configurable to power good of any selected rails
- Open-drain interrupt
output pin
- I2C interface supports standard mode
(100kHz), fast mode (400kHz), and fast mode plus (1MHz)
