SMPS REGULATORS |
1 |
FBGND2 |
I |
Remote negative feedback sense for BUCK2 controller. Connect to
negative terminal of output capacitor. Connect to ground when not in
use. |
2 |
FBVOUT2 |
I |
Remote positive feedback sense for BUCK2 controller. Connect to
positive terminal of output capacitor. Connect to ground when not in
use. |
3 |
DRVH2 |
O |
High-side gate driver output for BUCK2 controller. Leave floating
when not in use. |
4 |
SW2 |
I |
Switch node connection for BUCK2 controller. Connect to ground when
not in use. |
5 |
BOOT2 |
I |
Bootstrap pin for BUCK2 controller. Connect a 100nF ceramic
capacitor between this pin and SW2 pin. Leave floating when not in
use. |
6 |
PGNDSNS2 |
I |
Power GND connection for BUCK2. Connect to ground terminal of
external low-side FET. Connect to ground when not in use. |
7 |
DRVL2 |
O |
Low-side gate driver output for BUCK2 controller. Leave floating
when not in use. |
8 |
DRV5V_2_A1 |
I |
5V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a
2.2µF (typical) ceramic capacitor. Shorted on board to LDO5P0 pin
typically. Bypass not required if BUCK2 and LDOA1 are not in
use. |
10 |
LX3 |
O |
Switch node connection for BUCK3 converter. Leave floating when not
in use. |
11 |
PVIN3 |
I |
Power input to BUCK3 converter. Bypass to ground with a 10µF
(typical) ceramic capacitor. Bypass not required if BUCK3 is not in
use. |
12 |
FB3 |
I |
Remote feedback sense for BUCK3 converter. Connect to positive
terminal of output capacitor. Connect to ground when not in
use. |
20 |
LX5 |
O |
Switch node connection for BUCK5 converter. Leave floating when not
in use. |
21 |
PVIN5 |
I |
Power input to BUCK5 converter. Bypass to ground with a 10µF
(typical) ceramic capacitor. Bypass not required if BUCK5 is not in
use. |
22 |
FB5 |
I |
Remote feedback sense for BUCK5 converter. Connect to positive
terminal of output capacitor. Connect to ground when not in
use. |
23 |
FB4 |
I |
Remote feedback sense for BUCK4 converter. Connect to positive
terminal of output capacitor. Connect to ground when not in
use. |
24 |
PVIN4 |
I |
Power input to BUCK4 converter. Bypass to ground with a 10µF
(typical) ceramic capacitor. Bypass not required if BUCK4 is not in
use. |
25 |
LX4 |
O |
Switch node connection for BUCK4 converter. Leave floating when not
in use. |
29 |
FBVOUT1 |
I |
Remote feedback sense for BUCK1 controller. Connect to positive
terminal of output capacitor. Connect to ground when not in
use. |
30 |
ILIM1 |
I |
Current limit set pin for BUCK1 controller. Fit a resistor from
this pin to ground to set current limit of external low-side FET.
Connect to ground when BUCK1 not in use. |
33 |
DRVH1 |
O |
High-side gate driver output for BUCK1 controller. Leave floating
when not in use. |
34 |
SW1 |
I |
Switch node connection for BUCK1 controller. Connect to ground when
not in use. |
35 |
BOOT1 |
I |
Bootstrap pin for BUCK1 controller. Connect a 100nF ceramic
capacitor between this pin and SW1 pin. Leave floating when not in
use. |
36 |
PGNDSNS1 |
I |
Power GND connection for BUCK1. Connect to ground terminal of
external low-side FET. Connect to ground when not in use. |
37 |
DRVL1 |
O |
Low-side gate driver output for BUCK1 controller. Leave floating
when not in use. |
38 |
DRV5V_1_6 |
I |
5V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a
2.2µF (typical) ceramic capacitor. Shorted on board to LDO5P0 pin
typically. Bypass not required if BUCK1 and BUCK6 are not in
use. |
39 |
DRVL6 |
O |
Low-side gate driver output for BUCK6 controller. Leave floating
when not in use. |
40 |
PGNDSNS6 |
I |
Power GND connection for BUCK6. Connect to ground terminal of
external low-side FET. Connect to ground when not in use. |
41 |
BOOT6 |
I |
Bootstrap pin for BUCK6 controller. Connect a 100nF ceramic
capacitor between this pin and SW6 pin. Leave floating when not in
use. |
42 |
SW6 |
I |
Switch node connection for BUCK6 controller. Connect to ground when
not in use. |
43 |
DRVH6 |
O |
High-side gate driver output for BUCK6 controller. Leave floating
when not in use. |
44 |
FBVOUT6 |
I |
Remote feedback sense for BUCK6 controller and reference voltage
for VTT LDO regulation. Connect to positive terminal of output
capacitor. Connect to ground when not in use. |
45 |
ILIM6 |
I |
Current limit set pin for BUCK6 controller. Fit a resistor from
this pin to ground to set current limit of external low-side FET.
Connect to ground when BUCK6 not in use. |
64 |
ILIM2 |
I |
Current limit set pin for BUCK2 controller. Fit a resistor from
this pin to ground to set current limit of external low-side FET.
Connect to ground when BUCK2 not in use. |
LDO AND LOAD
SWITCHES |
9 |
LDOA1 |
O |
LDOA1 output. Bypass to ground with a 4.7µF (typical) ceramic
capacitor. Leave floating when not in use. |
17 |
SWB1 |
O |
Output of load switch B1. Bypass to ground with a 0.1µF (typical)
ceramic capacitor. Leave floating when not in use. |
18 |
PVINSWB1_B2 |
I |
Power supply to load switch B1 and B2. Bypass to ground with a 1µF
(typical) ceramic capacitor to improve transient performance.
Connect to ground when not in use. |
19 |
SWB2 |
O |
Output of load switch B2. Bypass to ground with a 0.1µF (typical)
ceramic capacitor. Leave floating when not in use. |
31 |
SWA1 |
O |
Output of load switch A1. Bypass to ground with a 0.1µF (typical)
ceramic capacitor. Leave floating when not in use. |
32 |
PVINSWA1 |
I |
Power supply to load switch A1. Bypass to ground with a 1µF
(typical) ceramic capacitor to improve transient performance.
Connect to ground when not in use. |
46 |
PVINVTT |
I |
Power supply to VTT LDO. Bypass to ground with a 10µF (minimum)
ceramic capacitor. Bypass not required if VTT LDO is not in
use. |
47 |
VTT |
O |
Output of load VTT LDO. Bypass to ground with 2× 22µF (minimum)
ceramic capacitors. Leave floating when not in use. |
48 |
VTTFB |
I |
Remote feedback sense for VTT LDO. Connect to positive terminal of
output capacitor. Connect to ground when not in use. |
49 |
LDOA3 |
O |
Output of LDOA3. Bypass to ground with a 4.7µF (typical) ceramic
capacitor. Leave floating when not in use. |
50 |
PVINLDOA2_A3 |
I |
Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7µF
(typical) ceramic capacitor. Connect to ground when not in
use. |
51 |
LDOA2 |
O |
Output of LDOA2. Bypass to ground with a 4.7µF (typical) ceramic
capacitor. Leave floating when not in use. |
54 |
LDO3P3 |
O |
Output of 3.3V internal LDO. Bypass to ground with a 4.7µF
(typical) ceramic capacitor. |
56 |
LDO5P0 |
O |
Output of 5V internal LDO or an internal switch that connects this
pin to V5ANA. Bypass to ground with a 4.7µF (typical) ceramic
capacitor. |
57 |
V5ANA |
I |
Bias used by converters (BUCK3, BUCK4, and BUCK5) for regulation.
Must be same supply as PVINx. Also has an internal load switch that
connects this pin to LDO5P0 pin if 5V is used. Bypass this pin with
an optional ceramic capacitor to improve transient
performance. |
INTERFACE |
13 |
CTL1 |
I |
Active-high VR enable pin. A group of VRs can be assigned to be
enabled at assertion or disabled at deassertion of this pin. |
14 |
CTL6/SLPENB2 |
I |
Active-high VR enable pin. A group of VRs can be assigned to be
enabled at assertion or disabled at deassertion of this pin.
Alternatively, when configured to active-low sleep enable, a group
of VRs chosen can be entered into (L) or out of (H) sleep state
where their output voltages may be different from those in normal
state. |
15 |
IRQB |
O |
Open-drain output interrupt pin. Refer to Section 6.11.4, IRQ: PMIC
Interrupt Register, for definitions. For programming, this pin must be
supplied with a stable 7V supply to burn the OTP memory.
Recommend bypassing to ground with a 1µF (typical) ceramic
capacitor. Do not back-drive any pull-up on this output if
programming.(1) |
16 |
GPO1 |
O |
General purpose output that can be configured to either open-drain
or push-pull arrangement. Regardless of the configuration, the pin
can be programmed either to reflect Power Good status of VRs of any
choice or to be controlled by an I2C register bit by the
user, which then can be used as an enable signal to an external
VR. |
26 |
GPO2 |
O |
General purpose output that can be configured to either open-drain
or push-pull arrangement. Regardless of the configuration, the pin
can be programmed either to reflect Power Good status of VRs of any
choice or to be controlled by an I2C register bit by the
user, which then can be used as an enable signal to an external
VR. |
27 |
GPO3 |
O |
General purpose output that can be configured to either open-drain
or push-pull arrangement. Regardless of the configuration, the pin
can be programmed either to reflect Power Good status of VRs of any
choice or to be controlled by an I2C register bit by the
user, which then can be used as an enable signal to an external
VR. |
28 |
GPO4 |
O |
Open-drain output that can be configured to reflect Power Good
status of VRs of any choice or to be controlled by an I2C
register bit by the user, which then can be used as an enable signal
to an external VR. |
58 |
CLK |
I |
I2C clock |
59 |
DATA |
I/O |
I2C data |
60 |
CTL2 |
I |
Active-high VR enable pin. A group of VRs can be assigned to be
enabled at assertion or disabled at deassertion of this pin. |
61 |
CTL3/SLPENB1 |
I |
Active-high VR enable pin. A group of VRs can be assigned to be
enabled at assertion or disabled at deassertion of this pin.
Alternatively, when configured to active-low sleep enable, a group
of VRs chosen can be entered into (L) or out of (H) sleep state
where their output voltages may be different from those in normal
state. |
62 |
CTL4 |
I |
Active-high VR enable pin. A group of VRs can be assigned to be
enabled at assertion or disabled at deassertion of this pin. For programming, this pin must be
supplied with a stable 7V supply to enter the programming state.
Because of this requirement, CTL4 is generally not used to
enable or disable regulators for the TPS650861 to avoid enabling
rails during programming or damaging devices connected to CTL4.
No bypass capacitor is needed for this pin.(1) |
63 |
CTL5 |
I |
Active-high VR enable pin. A group of VRs can be assigned to be
enabled at assertion or disabled at deassertion of this pin. |
REFERENCE |
52 |
AGND |
— |
Analog ground. Do not connect to the thermal pad ground on top
layer. Connect to ground of VREF capacitor. |
53 |
VREF |
O |
Band-gap reference output. Stabilize it by connecting a 100nF
(typical) ceramic capacitor between this pin and quiet
ground. |
55 |
VSYS |
I |
System voltage detection and input to internal LDOs (3.3V and 5V).
Bypass to ground with a 1µF (typical) ceramic capacitor. |
THERMAL PAD |
— |
Thermal pad (PGND) |
— |
Connect to PCB ground plane using multiple vias for good thermal
and electrical performance. |