SWCS142A July 2018 – January 2025 TPS650861
PRODUCTION DATA
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
Bit Name | RESERVED | RESERVED | BUCK2_ STEP_SIZE | BUCK2_ PINEN_ SEL[2] | BUCK2_ PINEN_ SEL[1] | BUCK2_ PINEN_ SEL[0] | BUCK2_ SWB2_LDOA1_PGM | BUCK2_ SWB1_PGM |
TPS65086100 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
5 | BUCK2_STEP_SIZE(1) | R/W | X | BUCK2 step size. 0: 10 mV 1: 25 mV |
4:2 | BUCK2_PINEN_SEL[2:0] | R/W | X | BUCK2 Enable pin select. 000: CTL1 001: CTL2 010: CTL5 011: CTL4 100: CTL3 101: CTL3 and CTL4 110: CTL6 111: 1 is inserted into CTL MUX. No pin is required to enable. |
1 | BUCK2_SWB2_LDOA1_PGM | R/W | X | SWB2_LDOA1 PGOOD masked 0: SWB2_LDOA1 PGOOD is part of Enable Logic. 1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic. |
0 | BUCK2_SWB1_PGM | R/W | X | SWB1 PGOOD masked 0: SWB1 PGOOD is part of Enable Logic. 1: SWB1 PGOOD is masked and is not part of enable logic. |