SWCS142A July 2018 – January 2025 TPS650861
PRODUCTION DATA
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
Bit Name | BUCK6_ VSEL_ OPTION | RESERVED | RESERVED | LDOA3_ PINEN_ SEL[2] | LDOA3_ PINEN_ SEL[1] | LDOA3_ PINEN_ SEL[0] | LDOA3_ SWB2_LDOA1_PGM | LDOA3_ SWB1_PGM |
TPS65086100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | BUCK6_VSEL_OPTION | R/W | X | Determines whether high level on CTRL2 can set BUCK6 to 1.2 V. If step size is 25 mV the voltage will be 2.4 V. SLP pin will override this voltage. 0: CTRL2 has no effect. 1: CTRL2 controls output voltage. |
4:2 | LDOA3_PINEN_SEL[2:0] | R/W | X | LDOA3 Enable pin select. 000: CTL1 001: CTL2 010: CTL5 011: CTL4 100: CTL3 101: CTL3 and CTL4 110: CTL6 111: 1 is inserted into CTL MUX. No pin is required to enable. |
1 | LDOA3_SWB2_LDOA1_PGM | R/W | X | SWB2_LDOA1 PGOOD masked 0: SWB2_LDOA1 PGOOD is part of Enable Logic. 1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic. |
0 | LDOA3_SWB1_PGM | R/W | X | SWB1 PGOOD masked 0: SWB1 PGOOD is part of Enable Logic. 1: SWB1 PGOOD is masked and is not part of enable logic. |