SWCU185G January   2018  – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  3. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4F
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Sensor Controller
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  4. 3 Arm® Cortex®-M4F Processor
    1. 3.1 Arm® Cortex®-M4F Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Floating Point Unit (FPU)
      5. 3.3.5 Memory Protection Unit (MPU)
      6. 3.3.6 Arm® Cortex®-M4F System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4F Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4F Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Floating Point Unit (FPU)
      1. 3.7.1 About the FPU
      2. 3.7.2 FPU Functional Description
        1. 3.7.2.1 FPU Views of the Register Bank
        2. 3.7.2.2 Modes of Operation
          1. 3.7.2.2.1 Full-Compliance Mode
          2. 3.7.2.2.2 Flush-to-Zero Mode
          3. 3.7.2.2.3 Default NaN Mode
        3. 3.7.2.3 FPU Instruction Set
        4. 3.7.2.4 Compliance With the IEEE 754 Standard
        5. 3.7.2.5 Complete Implementation of the IEEE 754 Standard
        6. 3.7.2.6 IEEE 754 Standard Implementation Choices
          1. 3.7.2.6.1 NaN Handling
          2. 3.7.2.6.2 Comparisons
          3. 3.7.2.6.3 Underflow
        7. 3.7.2.7 Exceptions
      3. 3.7.3 FPU Programmers Model
        1. 3.7.3.1 Enabling the FPU
          1. 3.7.3.1.1 Enabling the FPU
    8. 3.8 Memory Protection Unit (MPU)
      1. 3.8.1 About the MPU
      2. 3.8.2 MPU Functional Description
      3. 3.8.3 MPU Programmers Model
    9. 3.9 Arm® Cortex®-M4F Processor Registers
      1. 3.9.1 CPU_DWT Registers
      2. 3.9.2 CPU_FPB Registers
      3. 3.9.3 CPU_ITM Registers
      4. 3.9.4 CPU_SCS Registers
      5. 3.9.5 CPU_TPIU Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Arm® Cortex®-M4F Peripherals
    1. 5.1 Arm® Cortex®-M4F Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  7. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  8. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  9. 8 Power, Reset, and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 DDI_0_OSC Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  10. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  11. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM_MMR Registers
      2. 10.7.2 SRAM Registers
  12. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  13. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  14. 13Cryptography
    1. 13.1 AES and Hash Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master PROT Enable
          1. 13.5.4.2.1 Master PROT-Privileged Access-Enable
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
        5. 13.5.6.5 Hash Engine
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Hashing
        1. 13.7.3.1 Data Format and Byte Order
        2. 13.7.3.2 Basic Hash With Data From DMA
          1. 13.7.3.2.1 New Hash Session With Digest Read Through Slave
          2. 13.7.3.2.2 New Hash Session With Digest to External Memory
          3. 13.7.3.2.3 Resumed Hash Session
        3. 13.7.3.3 HMAC
          1. 13.7.3.3.1 Secure HMAC
        4. 13.7.3.4 Alternative Basic Hash Where Data Originates From Slave Interface
          1. 13.7.3.4.1 New Hash Session
          2. 13.7.3.4.2 Resumed Hash Session
      4. 13.7.4 Encryption and Decryption
        1. 13.7.4.1 Data Format and Byte Order
        2. 13.7.4.2 Key Store
          1. 13.7.4.2.1 Load Keys From External Memory
        3. 13.7.4.3 Basic AES Modes
          1. 13.7.4.3.1 AES-ECB
          2. 13.7.4.3.2 AES-CBC
          3. 13.7.4.3.3 AES-CTR
          4. 13.7.4.3.4 Programming Sequence With DMA Data
        4. 13.7.4.4 CBC-MAC
          1. 13.7.4.4.1 Programming Sequence for CBC-MAC
        5. 13.7.4.5 AES-CCM
          1. 13.7.4.5.1 Programming Sequence for AES-CCM
        6. 13.7.4.6 AES-GCM
          1. 13.7.4.6.1 Programming Sequence for AES-GCM
      5. 13.7.5 Exceptions Handling
        1. 13.7.5.1 Soft Reset
        2. 13.7.5.2 External Port Errors
        3. 13.7.5.3 Key Store Errors
          1. 13.7.5.3.1 PKA Engine
          2. 13.7.5.3.2 Functional Description
            1. 13.7.5.3.2.1 Module Architecture
          3. 13.7.5.3.3 PKA RAM
            1. 13.7.5.3.3.1 PKCP Operations
            2. 13.7.5.3.3.2 Sequencer Operations
              1. 13.7.5.3.3.2.1 Modular Exponentiation Operations
              2. 13.7.5.3.3.2.2 Modular Inversion Operation
              3. 13.7.5.3.3.2.3 Performance
              4. 13.7.5.3.3.2.4 ECC Operations
              5. 13.7.5.3.3.2.5 Performance
              6. 13.7.5.3.3.2.6 ExpMod Performance
              7. 13.7.5.3.3.2.7 Modular Inversion Performance
              8. 13.7.5.3.3.2.8 ECC Operation Performance
            3. 13.7.5.3.3.3 Sequencer ROM Behavior and Interfaces
            4. 13.7.5.3.3.4 Register Configurations
            5. 13.7.5.3.3.5 Operation Sequence
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  15. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 UDMA Registers
  17. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  18. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  19. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  20. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 AIODIO
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 SMPH
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPIM
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
              1. 20.4.7.2.5.1.1 Timer Period and Pulse Width Capture
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.2.1 Center-Aligned PWM Generation by Channel 0
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.3.1 Edge-Aligned PWM Generation by Channel 0
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 COMPA
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 COMPB
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference DAC
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 ISRC
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  24. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

12.4.1 FCFG1 Registers

Table 12-25 lists the memory-mapped registers for the FCFG1 registers. All register offset addresses not listed in Table 12-25 should be considered as reserved locations and the register contents should not be modified.

Table 12-25 FCFG1 Registers
OffsetAcronymRegister NameSection
A0hMISC_CONF_1Misc configurationsMISC_CONF_1 Register (Offset = A0h) [Reset = FFFFFF00h]
A4hMISC_CONF_2InternalMISC_CONF_2 Register (Offset = A4h) [Reset = FFFFFF00h]
B0hHPOSC_MEAS_5InternalHPOSC_MEAS_5 Register (Offset = B0h) [Reset = 00000000h]
B4hHPOSC_MEAS_4InternalHPOSC_MEAS_4 Register (Offset = B4h) [Reset = 00000000h]
B8hHPOSC_MEAS_3InternalHPOSC_MEAS_3 Register (Offset = B8h) [Reset = 00000000h]
BChHPOSC_MEAS_2InternalHPOSC_MEAS_2 Register (Offset = BCh) [Reset = 00000000h]
C0hHPOSC_MEAS_1InternalHPOSC_MEAS_1 Register (Offset = C0h) [Reset = 00000000h]
C4hCONFIG_CC26_FEInternalCONFIG_CC26_FE Register (Offset = C4h) [Reset = 70000F00h]
C8hCONFIG_CC13_FEInternalCONFIG_CC13_FE Register (Offset = C8h) [Reset = 70000F00h]
CChCONFIG_RF_COMMONInternalCONFIG_RF_COMMON Register (Offset = CCh) [Reset = 81C0014Dh]
D0hCONFIG_SYNTH_DIV2_CC26_2G4InternalCONFIG_SYNTH_DIV2_CC26_2G4 Register (Offset = D0h) [Reset = 0000001Fh]
D4hCONFIG_SYNTH_DIV2_CC13_2G4InternalCONFIG_SYNTH_DIV2_CC13_2G4 Register (Offset = D4h) [Reset = 0000001Fh]
D8hCONFIG_SYNTH_DIV2_CC26_1GInternalCONFIG_SYNTH_DIV2_CC26_1G Register (Offset = D8h) [Reset = 0000001Fh]
DChCONFIG_SYNTH_DIV2_CC13_1GInternalCONFIG_SYNTH_DIV2_CC13_1G Register (Offset = DCh) [Reset = 0000001Fh]
E0hCONFIG_SYNTH_DIV4_CC26InternalCONFIG_SYNTH_DIV4_CC26 Register (Offset = E0h) [Reset = 0000001Fh]
E4hCONFIG_SYNTH_DIV4_CC13InternalCONFIG_SYNTH_DIV4_CC13 Register (Offset = E4h) [Reset = 0000001Fh]
E8hCONFIG_SYNTH_DIV5InternalCONFIG_SYNTH_DIV5 Register (Offset = E8h) [Reset = 0000001Fh]
EChCONFIG_SYNTH_DIV6_CC26InternalCONFIG_SYNTH_DIV6_CC26 Register (Offset = ECh) [Reset = 0000001Fh]
F0hCONFIG_SYNTH_DIV6_CC13InternalCONFIG_SYNTH_DIV6_CC13 Register (Offset = F0h) [Reset = 0000001Fh]
F4hCONFIG_SYNTH_DIV10InternalCONFIG_SYNTH_DIV10 Register (Offset = F4h) [Reset = 0000001Fh]
F8hCONFIG_SYNTH_DIV12_CC26InternalCONFIG_SYNTH_DIV12_CC26 Register (Offset = F8h) [Reset = 0000001Fh]
FChCONFIG_SYNTH_DIV12_CC13InternalCONFIG_SYNTH_DIV12_CC13 Register (Offset = FCh) [Reset = 0000001Fh]
100hCONFIG_SYNTH_DIV15InternalCONFIG_SYNTH_DIV15 Register (Offset = 100h) [Reset = 0000001Fh]
104hCONFIG_SYNTH_DIV30InternalCONFIG_SYNTH_DIV30 Register (Offset = 104h) [Reset = 0000001Fh]
164hFLASH_NUMBERFlash informationFLASH_NUMBER Register (Offset = 164h) [Reset = 00000000h]
16ChFLASH_COORDINATEFlash informationFLASH_COORDINATE Register (Offset = 16Ch) [Reset = 00000000h]
170hFLASH_E_PInternalFLASH_E_P Register (Offset = 170h) [Reset = 4C644C64h]
174hFLASH_C_E_P_RInternalFLASH_C_E_P_R Register (Offset = 174h) [Reset = 0A0A2000h]
178hFLASH_P_R_PVInternalFLASH_P_R_PV Register (Offset = 178h) [Reset = 02C10200h]
17ChFLASH_EH_SEQInternalFLASH_EH_SEQ Register (Offset = 17Ch) [Reset = 0200F000h]
180hFLASH_VHV_EInternalFLASH_VHV_E Register (Offset = 180h) [Reset = 00000001h]
184hFLASH_PPInternalFLASH_PP Register (Offset = 184h) [Reset = 00000014h]
188hFLASH_PROG_EPInternalFLASH_PROG_EP Register (Offset = 188h) [Reset = 0FA00010h]
18ChFLASH_ERA_PWInternalFLASH_ERA_PW Register (Offset = 18Ch) [Reset = 00000FA0h]
190hFLASH_VHVInternalFLASH_VHV Register (Offset = 190h) [Reset = 00000004h]
194hFLASH_VHV_PVInternalFLASH_VHV_PV Register (Offset = 194h) [Reset = 00080001h]
198hFLASH_VInternalFLASH_V Register (Offset = 198h) [Reset = 00000000h]
294hUSER_IDUser Identification.USER_ID Register (Offset = 294h) [Reset = 30000000h]
2B0hFLASH_OTP_DATA3InternalFLASH_OTP_DATA3 Register (Offset = 2B0h) [Reset = 00110003h]
2B4hANA2_TRIMInternalANA2_TRIM Register (Offset = 2B4h) [Reset = 8240787Fh]
2B8hLDO_TRIMInternalLDO_TRIM Register (Offset = 2B8h) [Reset = E0F8E0FBh]
2E8hMAC_BLE_0MAC BLE Address 0MAC_BLE_0 Register (Offset = 2E8h) [Reset = 00000000h]
2EChMAC_BLE_1MAC BLE Address 1MAC_BLE_1 Register (Offset = 2ECh) [Reset = 00000000h]
2F0hMAC_15_4_0MAC IEEE 802.15.4 Address 0MAC_15_4_0 Register (Offset = 2F0h) [Reset = 00000000h]
2F4hMAC_15_4_1MAC IEEE 802.15.4 Address 1MAC_15_4_1 Register (Offset = 2F4h) [Reset = 00000000h]
308hFLASH_OTP_DATA4InternalFLASH_OTP_DATA4 Register (Offset = 308h) [Reset = 98989F9Fh]
30ChMISC_TRIMMiscellaneous Trim ParametersMISC_TRIM Register (Offset = 30Ch) [Reset = FFFE003Bh]
310hRCOSC_HF_TEMPCOMPInternalRCOSC_HF_TEMPCOMP Register (Offset = 310h) [Reset = 00000003h]
318hICEPICK_DEVICE_IDIcePick Device IdentificationICEPICK_DEVICE_ID Register (Offset = 318h) [Reset = 3BB4102Fh]
31ChFCFG1_REVISIONFactory Configuration (FCFG1) RevisionFCFG1_REVISION Register (Offset = 31Ch) [Reset = 0000002Ah]
320hMISC_OTP_DATAMisc OTP DataMISC_OTP_DATA Register (Offset = 320h) [Reset = 0000CFFFh]
344hIOCONFIO ConfigurationIOCONF Register (Offset = 344h) [Reset = FFFFFF00h]
34ChCONFIG_IF_ADCInternalCONFIG_IF_ADC Register (Offset = 34Ch) [Reset = 3460F400h]
350hCONFIG_OSC_TOPInternalCONFIG_OSC_TOP Register (Offset = 350h) [Reset = DC07FC00h]
35ChSOC_ADC_ABS_GAINAUX_ADC Gain in Absolute Reference ModeSOC_ADC_ABS_GAIN Register (Offset = 35Ch) [Reset = 00000000h]
360hSOC_ADC_REL_GAINAUX_ADC Gain in Relative Reference ModeSOC_ADC_REL_GAIN Register (Offset = 360h) [Reset = 00000000h]
368hSOC_ADC_OFFSET_INTAUX_ADC Temperature Offsets in Absolute Reference ModeSOC_ADC_OFFSET_INT Register (Offset = 368h) [Reset = 00000000h]
36ChSOC_ADC_REF_TRIM_AND_OFFSET_EXTInternalSOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [Reset = 0000C080h]
370hAMPCOMP_TH1InternalAMPCOMP_TH1 Register (Offset = 370h) [Reset = FF7B828Eh]
374hAMPCOMP_TH2InternalAMPCOMP_TH2 Register (Offset = 374h) [Reset = 6B8B0303h]
378hAMPCOMP_CTRL1InternalAMPCOMP_CTRL1 Register (Offset = 378h) [Reset = FF483F47h]
37ChANABYPASS_VALUE2InternalANABYPASS_VALUE2 Register (Offset = 37Ch) [Reset = FFFFC3FFh]
388hVOLT_TRIMInternalVOLT_TRIM Register (Offset = 388h) [Reset = E0E0E0E0h]
38ChOSC_CONFOSC ConfigurationOSC_CONF Register (Offset = 38Ch) [Reset = F00900E6h]
390hFREQ_OFFSETInternalFREQ_OFFSET Register (Offset = 390h) [Reset = 00000000h]
398hMISC_OTP_DATA_1InternalMISC_OTP_DATA_1 Register (Offset = 398h) [Reset = E08403F8h]
3D0hSHDW_DIE_ID_0Shadow of EFUSE:DIE_ID_0 registerSHDW_DIE_ID_0 Register (Offset = 3D0h) [Reset = 00000000h]
3D4hSHDW_DIE_ID_1Shadow of EFUSE:DIE_ID_1 registerSHDW_DIE_ID_1 Register (Offset = 3D4h) [Reset = 00000000h]
3D8hSHDW_DIE_ID_2Shadow of EFUSE:DIE_ID_2 registerSHDW_DIE_ID_2 Register (Offset = 3D8h) [Reset = 00000000h]
3DChSHDW_DIE_ID_3Shadow of EFUSE:DIE_ID_3 registerSHDW_DIE_ID_3 Register (Offset = 3DCh) [Reset = 00000000h]
3F8hSHDW_OSC_BIAS_LDO_TRIMInternalSHDW_OSC_BIAS_LDO_TRIM Register (Offset = 3F8h) [Reset = 00000000h]
3FChSHDW_ANA_TRIMInternalSHDW_ANA_TRIM Register (Offset = 3FCh) [Reset = 00000000h]
408hOSC_CONF1Oscillator configurationOSC_CONF1 Register (Offset = 408h) [Reset = FFFF0000h]
40ChDAC_BIAS_CNFInternalDAC_BIAS_CNF Register (Offset = 40Ch) [Reset = FFFC00FFh]
418hTFW_PROBEInternalTFW_PROBE Register (Offset = 418h) [Reset = 00000000h]
41ChTFW_FTInternalTFW_FT Register (Offset = 41Ch) [Reset = 00000000h]
420hDAC_CAL0InternalDAC_CAL0 Register (Offset = 420h) [Reset = 00000000h]
424hDAC_CAL1InternalDAC_CAL1 Register (Offset = 424h) [Reset = 00000000h]
428hDAC_CAL2InternalDAC_CAL2 Register (Offset = 428h) [Reset = 00000000h]
42ChDAC_CAL3InternalDAC_CAL3 Register (Offset = 42Ch) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Table 12-26 shows the codes that are used for access types in this section.

Table 12-26 FCFG1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

12.4.1.1 MISC_CONF_1 Register (Offset = A0h) [Reset = FFFFFF00h]

MISC_CONF_1 is shown in Figure 12-23 and described in Table 12-27.

Return to the Summary Table.

Misc configurations

Figure 12-23 MISC_CONF_1 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDDEVICE_MINOR_REV
R-0hR-X
Table 12-27 MISC_CONF_1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0DEVICE_MINOR_REVRXHW minor revision number (a value of 0xFF shall be treated equally to 0x00).
Any test of this field by SW should be implemented as a 'greater or equal' comparison as signed integer.
Value may change without warning.

Default value holds log information from production test.

12.4.1.2 MISC_CONF_2 Register (Offset = A4h) [Reset = FFFFFF00h]

MISC_CONF_2 is shown in Figure 12-24 and described in Table 12-28.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-24 MISC_CONF_2 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDHPOSC_COMP_P3
R-0hR-X
Table 12-28 MISC_CONF_2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0HPOSC_COMP_P3RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.3 HPOSC_MEAS_5 Register (Offset = B0h) [Reset = 00000000h]

HPOSC_MEAS_5 is shown in Figure 12-25 and described in Table 12-29.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-25 HPOSC_MEAS_5 Register
31302928272625242322212019181716
HPOSC_D5
R-X
1514131211109876543210
HPOSC_T5HPOSC_DT5
R-XR-X
Table 12-29 HPOSC_MEAS_5 Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_D5RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

15-8HPOSC_T5RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

7-0HPOSC_DT5RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

12.4.1.4 HPOSC_MEAS_4 Register (Offset = B4h) [Reset = 00000000h]

HPOSC_MEAS_4 is shown in Figure 12-26 and described in Table 12-30.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-26 HPOSC_MEAS_4 Register
31302928272625242322212019181716
HPOSC_D4
R-X
1514131211109876543210
HPOSC_T4HPOSC_DT4
R-XR-X
Table 12-30 HPOSC_MEAS_4 Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_D4RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

15-8HPOSC_T4RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

7-0HPOSC_DT4RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

12.4.1.5 HPOSC_MEAS_3 Register (Offset = B8h) [Reset = 00000000h]

HPOSC_MEAS_3 is shown in Figure 12-27 and described in Table 12-31.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-27 HPOSC_MEAS_3 Register
31302928272625242322212019181716
HPOSC_D3
R-X
1514131211109876543210
HPOSC_T3HPOSC_DT3
R-XR-X
Table 12-31 HPOSC_MEAS_3 Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_D3RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

15-8HPOSC_T3RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

7-0HPOSC_DT3RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

12.4.1.6 HPOSC_MEAS_2 Register (Offset = BCh) [Reset = 00000000h]

HPOSC_MEAS_2 is shown in Figure 12-28 and described in Table 12-32.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-28 HPOSC_MEAS_2 Register
31302928272625242322212019181716
HPOSC_D2
R-X
1514131211109876543210
HPOSC_T2HPOSC_DT2
R-XR-X
Table 12-32 HPOSC_MEAS_2 Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_D2RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

15-8HPOSC_T2RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

7-0HPOSC_DT2RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

12.4.1.7 HPOSC_MEAS_1 Register (Offset = C0h) [Reset = 00000000h]

HPOSC_MEAS_1 is shown in Figure 12-29 and described in Table 12-33.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-29 HPOSC_MEAS_1 Register
31302928272625242322212019181716
HPOSC_D1
R-X
1514131211109876543210
HPOSC_T1HPOSC_DT1
R-XR-X
Table 12-33 HPOSC_MEAS_1 Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_D1RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

15-8HPOSC_T1RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

7-0HPOSC_DT1RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

12.4.1.8 CONFIG_CC26_FE Register (Offset = C4h) [Reset = 70000F00h]

CONFIG_CC26_FE is shown in Figure 12-30 and described in Table 12-34.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-30 CONFIG_CC26_FE Register
3130292827262524
IFAMP_IBLNA_IB
R-7hR-X
2322212019181716
IFAMP_TRIMCTL_PA0_TRIM
R-0hR-X
15141312111098
CTL_PA0_TRIMPATRIMCOMPLETE_NRSSITRIMCOMPLETE_NRESERVED
R-XR-XR-XR-0h
76543210
RSSI_OFFSET
R-X
Table 12-34 CONFIG_CC26_FE Register Field Descriptions
BitFieldTypeResetDescription
31-28IFAMP_IBR7hInternal. Only to be used through TI provided API.
27-24LNA_IBRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-19IFAMP_TRIMR0hInternal. Only to be used through TI provided API.
18-14CTL_PA0_TRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

13PATRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12RSSITRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-8RESERVEDR0hReserved
7-0RSSI_OFFSETRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.9 CONFIG_CC13_FE Register (Offset = C8h) [Reset = 70000F00h]

CONFIG_CC13_FE is shown in Figure 12-31 and described in Table 12-35.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-31 CONFIG_CC13_FE Register
3130292827262524
IFAMP_IBLNA_IB
R-7hR-X
2322212019181716
IFAMP_TRIMCTL_PA0_TRIM
R-0hR-X
15141312111098
CTL_PA0_TRIMPATRIMCOMPLETE_NRSSITRIMCOMPLETE_NRESERVED
R-XR-XR-XR-0h
76543210
RSSI_OFFSET
R-X
Table 12-35 CONFIG_CC13_FE Register Field Descriptions
BitFieldTypeResetDescription
31-28IFAMP_IBR7hInternal. Only to be used through TI provided API.
27-24LNA_IBRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-19IFAMP_TRIMR0hInternal. Only to be used through TI provided API.
18-14CTL_PA0_TRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

13PATRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12RSSITRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-8RESERVEDR0hReserved
7-0RSSI_OFFSETRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.10 CONFIG_RF_COMMON Register (Offset = CCh) [Reset = 81C0014Dh]

CONFIG_RF_COMMON is shown in Figure 12-32 and described in Table 12-36.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-32 CONFIG_RF_COMMON Register
3130292827262524
DISABLE_CORNER_CAPSLDO_TRIM_OUTPUTRESERVED
R-1hR-XR-0h
2322212019181716
RESERVEDPA20DBMTRIMCOMPLETE_NCTL_PA_20DBM_TRIM
R-0hR-XR-X
15141312111098
RFLDO_TRIM_OUTPUTQUANTCTLTHRES
R-XR-5h
76543210
QUANTCTLTHRESDACTRIM
R-5hR-Dh
Table 12-36 CONFIG_RF_COMMON Register Field Descriptions
BitFieldTypeResetDescription
31DISABLE_CORNER_CAPR1hInternal. Only to be used through TI provided API.
30-25SLDO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

24-22RESERVEDR0hReserved
21PA20DBMTRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.
20-16CTL_PA_20DBM_TRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-9RFLDO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.
8-6QUANTCTLTHRESR5hInternal. Only to be used through TI provided API.
5-0DACTRIMRDhInternal. Only to be used through TI provided API.

12.4.1.11 CONFIG_SYNTH_DIV2_CC26_2G4 Register (Offset = D0h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV2_CC26_2G4 is shown in Figure 12-33 and described in Table 12-37.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-33 CONFIG_SYNTH_DIV2_CC26_2G4 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-37 CONFIG_SYNTH_DIV2_CC26_2G4 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.12 CONFIG_SYNTH_DIV2_CC13_2G4 Register (Offset = D4h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV2_CC13_2G4 is shown in Figure 12-34 and described in Table 12-38.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-34 CONFIG_SYNTH_DIV2_CC13_2G4 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-38 CONFIG_SYNTH_DIV2_CC13_2G4 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.13 CONFIG_SYNTH_DIV2_CC26_1G Register (Offset = D8h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV2_CC26_1G is shown in Figure 12-35 and described in Table 12-39.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-35 CONFIG_SYNTH_DIV2_CC26_1G Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-39 CONFIG_SYNTH_DIV2_CC26_1G Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.14 CONFIG_SYNTH_DIV2_CC13_1G Register (Offset = DCh) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV2_CC13_1G is shown in Figure 12-36 and described in Table 12-40.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-36 CONFIG_SYNTH_DIV2_CC13_1G Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-40 CONFIG_SYNTH_DIV2_CC13_1G Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.15 CONFIG_SYNTH_DIV4_CC26 Register (Offset = E0h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV4_CC26 is shown in Figure 12-37 and described in Table 12-41.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-37 CONFIG_SYNTH_DIV4_CC26 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-41 CONFIG_SYNTH_DIV4_CC26 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.16 CONFIG_SYNTH_DIV4_CC13 Register (Offset = E4h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV4_CC13 is shown in Figure 12-38 and described in Table 12-42.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-38 CONFIG_SYNTH_DIV4_CC13 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-42 CONFIG_SYNTH_DIV4_CC13 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.17 CONFIG_SYNTH_DIV5 Register (Offset = E8h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV5 is shown in Figure 12-39 and described in Table 12-43.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-39 CONFIG_SYNTH_DIV5 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-43 CONFIG_SYNTH_DIV5 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.18 CONFIG_SYNTH_DIV6_CC26 Register (Offset = ECh) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV6_CC26 is shown in Figure 12-40 and described in Table 12-44.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-40 CONFIG_SYNTH_DIV6_CC26 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-44 CONFIG_SYNTH_DIV6_CC26 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.19 CONFIG_SYNTH_DIV6_CC13 Register (Offset = F0h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV6_CC13 is shown in Figure 12-41 and described in Table 12-45.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-41 CONFIG_SYNTH_DIV6_CC13 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-45 CONFIG_SYNTH_DIV6_CC13 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.20 CONFIG_SYNTH_DIV10 Register (Offset = F4h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV10 is shown in Figure 12-42 and described in Table 12-46.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-42 CONFIG_SYNTH_DIV10 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-46 CONFIG_SYNTH_DIV10 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.21 CONFIG_SYNTH_DIV12_CC26 Register (Offset = F8h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV12_CC26 is shown in Figure 12-43 and described in Table 12-47.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-43 CONFIG_SYNTH_DIV12_CC26 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-47 CONFIG_SYNTH_DIV12_CC26 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.22 CONFIG_SYNTH_DIV12_CC13 Register (Offset = FCh) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV12_CC13 is shown in Figure 12-44 and described in Table 12-48.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-44 CONFIG_SYNTH_DIV12_CC13 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-48 CONFIG_SYNTH_DIV12_CC13 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.23 CONFIG_SYNTH_DIV15 Register (Offset = 100h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV15 is shown in Figure 12-45 and described in Table 12-49.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-45 CONFIG_SYNTH_DIV15 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-49 CONFIG_SYNTH_DIV15 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.24 CONFIG_SYNTH_DIV30 Register (Offset = 104h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV30 is shown in Figure 12-46 and described in Table 12-50.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-46 CONFIG_SYNTH_DIV30 Register
3130292827262524
MIN_ALLOWED_RTRIMRFC_MDM_DEMIQMC0
R-XR-X
2322212019181716
RFC_MDM_DEMIQMC0
R-X
15141312111098
RFC_MDM_DEMIQMC0LDOVCO_TRIM_OUTPUT
R-XR-X
76543210
LDOVCO_TRIM_OUTPUTRFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRESERVED
R-XR-XR-0h
Table 12-50 CONFIG_SYNTH_DIV30 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

12.4.1.25 FLASH_NUMBER Register (Offset = 164h) [Reset = 00000000h]

FLASH_NUMBER is shown in Figure 12-47 and described in Table 12-51.

Return to the Summary Table.

Flash information

Figure 12-47 FLASH_NUMBER Register
313029282726252423222120191817161514131211109876543210
LOT_NUMBER
R-X
Table 12-51 FLASH_NUMBER Register Field Descriptions
BitFieldTypeResetDescription
31-0LOT_NUMBERRXNumber of the manufacturing lot that produced this unit.

Default value holds log information from production test.

12.4.1.26 FLASH_COORDINATE Register (Offset = 16Ch) [Reset = 00000000h]

FLASH_COORDINATE is shown in Figure 12-48 and described in Table 12-52.

Return to the Summary Table.

Flash information

Figure 12-48 FLASH_COORDINATE Register
313029282726252423222120191817161514131211109876543210
XCOORDINATEYCOORDINATE
R-XR-X
Table 12-52 FLASH_COORDINATE Register Field Descriptions
BitFieldTypeResetDescription
31-16XCOORDINATERXX coordinate of this unit on the wafer.

Default value holds log information from production test.

15-0YCOORDINATERXY coordinate of this unit on the wafer.

Default value holds log information from production test.

12.4.1.27 FLASH_E_P Register (Offset = 170h) [Reset = 4C644C64h]

FLASH_E_P is shown in Figure 12-49 and described in Table 12-53.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-49 FLASH_E_P Register
313029282726252423222120191817161514131211109876543210
PSUESUPVSUEVSU
R-4ChR-64hR-4ChR-64h
Table 12-53 FLASH_E_P Register Field Descriptions
BitFieldTypeResetDescription
31-24PSUR4ChInternal. Only to be used through TI provided API.
23-16ESUR64hInternal. Only to be used through TI provided API.
15-8PVSUR4ChInternal. Only to be used through TI provided API.
7-0EVSUR64hInternal. Only to be used through TI provided API.

12.4.1.28 FLASH_C_E_P_R Register (Offset = 174h) [Reset = 0A0A2000h]

FLASH_C_E_P_R is shown in Figure 12-50 and described in Table 12-54.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-50 FLASH_C_E_P_R Register
31302928272625242322212019181716
RVSUPV_ACCESS
R-AhR-Ah
1514131211109876543210
A_EXEZ_SETUPCVSU
R-2hR-0h
Table 12-54 FLASH_C_E_P_R Register Field Descriptions
BitFieldTypeResetDescription
31-24RVSURAhInternal. Only to be used through TI provided API.
23-16PV_ACCESSRAhInternal. Only to be used through TI provided API.
15-12A_EXEZ_SETUPR2hInternal. Only to be used through TI provided API.
11-0CVSUR0hInternal. Only to be used through TI provided API.

12.4.1.29 FLASH_P_R_PV Register (Offset = 178h) [Reset = 02C10200h]

FLASH_P_R_PV is shown in Figure 12-51 and described in Table 12-55.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-51 FLASH_P_R_PV Register
313029282726252423222120191817161514131211109876543210
PHRHPVHPVH2
R-2hR-C1hR-2hR-0h
Table 12-55 FLASH_P_R_PV Register Field Descriptions
BitFieldTypeResetDescription
31-24PHR2hInternal. Only to be used through TI provided API.
23-16RHRC1hInternal. Only to be used through TI provided API.
15-8PVHR2hInternal. Only to be used through TI provided API.
7-0PVH2R0hInternal. Only to be used through TI provided API.

12.4.1.30 FLASH_EH_SEQ Register (Offset = 17Ch) [Reset = 0200F000h]

FLASH_EH_SEQ is shown in Figure 12-52 and described in Table 12-56.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-52 FLASH_EH_SEQ Register
31302928272625242322212019181716
EHSEQ
R-2hR-0h
1514131211109876543210
VSTATSM_FREQUENCY
R-FhR-0h
Table 12-56 FLASH_EH_SEQ Register Field Descriptions
BitFieldTypeResetDescription
31-24EHR2hInternal. Only to be used through TI provided API.
23-16SEQR0hInternal. Only to be used through TI provided API.
15-12VSTATRFhInternal. Only to be used through TI provided API.
11-0SM_FREQUENCYR0hInternal. Only to be used through TI provided API.

12.4.1.31 FLASH_VHV_E Register (Offset = 180h) [Reset = 00000001h]

FLASH_VHV_E is shown in Figure 12-53 and described in Table 12-57.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-53 FLASH_VHV_E Register
313029282726252423222120191817161514131211109876543210
VHV_E_STARTVHV_E_STEP_HIGHT
R-0hR-1h
Table 12-57 FLASH_VHV_E Register Field Descriptions
BitFieldTypeResetDescription
31-16VHV_E_STARTR0hInternal. Only to be used through TI provided API.
15-0VHV_E_STEP_HIGHTR1hInternal. Only to be used through TI provided API.

12.4.1.32 FLASH_PP Register (Offset = 184h) [Reset = 00000014h]

FLASH_PP is shown in Figure 12-54 and described in Table 12-58.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-54 FLASH_PP Register
313029282726252423222120191817161514131211109876543210
PUMP_SUTRIM3P4MAX_PP
R-0hR-XR-14h
Table 12-58 FLASH_PP Register Field Descriptions
BitFieldTypeResetDescription
31-24PUMP_SUR0hInternal. Only to be used through TI provided API.
23-16TRIM3P4RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-0MAX_PPR14hInternal. Only to be used through TI provided API.

12.4.1.33 FLASH_PROG_EP Register (Offset = 188h) [Reset = 0FA00010h]

FLASH_PROG_EP is shown in Figure 12-55 and described in Table 12-59.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-55 FLASH_PROG_EP Register
313029282726252423222120191817161514131211109876543210
MAX_EPPROGRAM_PW
R-FA0hR-10h
Table 12-59 FLASH_PROG_EP Register Field Descriptions
BitFieldTypeResetDescription
31-16MAX_EPRFA0hInternal. Only to be used through TI provided API.
15-0PROGRAM_PWR10hInternal. Only to be used through TI provided API.

12.4.1.34 FLASH_ERA_PW Register (Offset = 18Ch) [Reset = 00000FA0h]

FLASH_ERA_PW is shown in Figure 12-56 and described in Table 12-60.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-56 FLASH_ERA_PW Register
313029282726252423222120191817161514131211109876543210
ERASE_PW
R-FA0h
Table 12-60 FLASH_ERA_PW Register Field Descriptions
BitFieldTypeResetDescription
31-0ERASE_PWRFA0hInternal. Only to be used through TI provided API.

12.4.1.35 FLASH_VHV Register (Offset = 190h) [Reset = 00000004h]

FLASH_VHV is shown in Figure 12-57 and described in Table 12-61.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-57 FLASH_VHV Register
31302928272625242322212019181716
RESERVEDTRIM13_PRESERVEDVHV_P
R-0hR-XR-0hR-X
1514131211109876543210
RESERVEDTRIM13_ERESERVEDVHV_E
R-0hR-XR-0hR-4h
Table 12-61 FLASH_VHV Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-24TRIM13_PRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-20RESERVEDR0hReserved
19-16VHV_PRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-12RESERVEDR0hReserved
11-8TRIM13_ERXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

7-4RESERVEDR0hReserved
3-0VHV_ER4hInternal. Only to be used through TI provided API.

12.4.1.36 FLASH_VHV_PV Register (Offset = 194h) [Reset = 00080001h]

FLASH_VHV_PV is shown in Figure 12-58 and described in Table 12-62.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-58 FLASH_VHV_PV Register
31302928272625242322212019181716
RESERVEDTRIM13_PVRESERVEDVHV_PV
R-0hR-XR-0hR-8h
1514131211109876543210
VCG2P5VINH
R-XR-1h
Table 12-62 FLASH_VHV_PV Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-24TRIM13_PVRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-20RESERVEDR0hReserved
19-16VHV_PVR8hInternal. Only to be used through TI provided API.
15-8VCG2P5RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

7-0VINHR1hInternal. Only to be used through TI provided API.

12.4.1.37 FLASH_V Register (Offset = 198h) [Reset = 00000000h]

FLASH_V is shown in Figure 12-59 and described in Table 12-63.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-59 FLASH_V Register
313029282726252423222120191817161514131211109876543210
VSL_PVWL_PV_READTRIM0P8
R-XR-XR-XR-X
Table 12-63 FLASH_V Register Field Descriptions
BitFieldTypeResetDescription
31-24VSL_PRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-16VWL_PRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-8V_READRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

7-0TRIM0P8RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.38 USER_ID Register (Offset = 294h) [Reset = 30000000h]

USER_ID is shown in Figure 12-60 and described in Table 12-64.

Return to the Summary Table.

User Identification.
Reading this register and the FCFG1:ICEPICK_DEVICE_ID register is the only supported way of identifying a device.
The value of this register will be written to AON_PMCTL:JTAGUSERCODE by boot FW while in safezone.

Figure 12-60 USER_ID Register
3130292827262524
PG_REVVERPARESERVED
R-3hR-XR-XR-0h
2322212019181716
CC13SEQUENCEPKG
R-XR-XR-X
15141312111098
PROTOCOLRESERVED
R-XR-0h
76543210
RESERVED
R-0h
Table 12-64 USER_ID Register Field Descriptions
BitFieldTypeResetDescription
31-28PG_REVR3hField used to distinguish revisions of the device
27-26VERRXVersion number.
0x0: Bits [25:12] of this register has the stated meaning.
Any other setting indicate a different encoding of these bits.

Default value differs depending on partnumber.

25PARX0: Does not support 20dBm PA
1: Supports 20dBM PA

Default value differs depending on partnumber.

24RESERVEDR0hReserved
23CC13RX0: CC26xx device type
1: CC13xx device type

Default value differs depending on partnumber.

22-19SEQUENCERXSequence.
Used to differentiate between marketing/orderable product where other fields of this register are the same (temp range, flash size, voltage range etc)

Default value differs depending on partnumber.

18-16PKGRXPackage type.
0x0: 4x4mm QFN (RHB) package
0x1: 5x5mm QFN (RSM) package
0x2: 7x7mm QFN (RGZ) package
0x3: Wafer sale package (naked die)
0x4: WCSP (YFV)
0x5: 7x7mm QFN package with Wettable Flanks
Other values are reserved for future use.
Packages available for a specific device are shown in the device datasheet.

Default value differs depending on partnumber.

15-12PROTOCOLRXProtocols supported.
0x1: BLE
0x2: RF4CE
0x4: Zigbee/6lowpan
0x8: Proprietary
More than one protocol can be supported on same device - values above are then combined.

Default value differs depending on partnumber.

11-0RESERVEDR0hReserved

12.4.1.39 FLASH_OTP_DATA3 Register (Offset = 2B0h) [Reset = 00110003h]

FLASH_OTP_DATA3 is shown in Figure 12-61 and described in Table 12-65.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-61 FLASH_OTP_DATA3 Register
3130292827262524
EC_STEP_SIZE
R-0h
2322212019181716
EC_STEP_SIZEDO_PRECONDMAX_EC_LEVELTRIM_1P7
R-0hR-0hR-4hR-1h
15141312111098
FLASH_SIZE
R-X
76543210
WAIT_SYSCODE
R-3h
Table 12-65 FLASH_OTP_DATA3 Register Field Descriptions
BitFieldTypeResetDescription
31-23EC_STEP_SIZER0hInternal. Only to be used through TI provided API.
22DO_PRECONDR0hInternal. Only to be used through TI provided API.
21-18MAX_EC_LEVELR4hInternal. Only to be used through TI provided API.
17-16TRIM_1P7R1hInternal. Only to be used through TI provided API.
15-8FLASH_SIZERXInternal. Only to be used through TI provided API.

Default value differs depending on partnumber.

7-0WAIT_SYSCODER3hInternal. Only to be used through TI provided API.

12.4.1.40 ANA2_TRIM Register (Offset = 2B4h) [Reset = 8240787Fh]

ANA2_TRIM is shown in Figure 12-62 and described in Table 12-66.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-62 ANA2_TRIM Register
3130292827262524
RCOSCHFCTRIMFRACT_ENRCOSCHFCTRIMFRACTRESERVEDSET_RCOSC_HF_FINE_RESISTOR
R-1hR-XR-0hR-X
2322212019181716
SET_RCOSC_HF_FINE_RESISTORATESTLF_UDIGLDO_IBIAS_TRIMNANOAMP_RES_TRIM
R-XR-1hR-X
15141312111098
NANOAMP_RES_TRIMRESERVEDDITHER_ENDCDC_IPEAK
R-XR-0hR-1hR-0h
76543210
DEAD_TIME_TRIMDCDC_LOW_EN_SELDCDC_HIGH_EN_SEL
R-1hR-7hR-7h
Table 12-66 ANA2_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31RCOSCHFCTRIMFRACT_ENR1hInternal. Only to be used through TI provided API.
30-26RCOSCHFCTRIMFRACTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

25RESERVEDR0hReserved
24-23SET_RCOSC_HF_FINE_RESISTORRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

22ATESTLF_UDIGLDO_IBIAS_TRIMR1hInternal. Only to be used through TI provided API.
21-15NANOAMP_RES_TRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

14-12RESERVEDR0hReserved
11DITHER_ENR1hInternal. Only to be used through TI provided API.
10-8DCDC_IPEAKR0hInternal. Only to be used through TI provided API.
7-6DEAD_TIME_TRIMR1hInternal. Only to be used through TI provided API.
5-3DCDC_LOW_EN_SELR7hInternal. Only to be used through TI provided API.
2-0DCDC_HIGH_EN_SELR7hInternal. Only to be used through TI provided API.

12.4.1.41 LDO_TRIM Register (Offset = 2B8h) [Reset = E0F8E0FBh]

LDO_TRIM is shown in Figure 12-63 and described in Table 12-67.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-63 LDO_TRIM Register
3130292827262524
RESERVEDVDDR_TRIM_SLEEP
R-0hR-X
2322212019181716
RESERVEDGLDO_CURSRC
R-0hR-0h
15141312111098
RESERVEDITRIM_DIGLDO_LOADITRIM_UDIGLDO
R-0hR-0hR-0h
76543210
RESERVEDVTRIM_DELTA
R-0hR-3h
Table 12-67 LDO_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24VDDR_TRIM_SLEEPRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-19RESERVEDR0hReserved
18-16GLDO_CURSRCR0hInternal. Only to be used through TI provided API.
15-13RESERVEDR0hReserved
12-11ITRIM_DIGLDO_LOADR0hInternal. Only to be used through TI provided API.
10-8ITRIM_UDIGLDOR0hInternal. Only to be used through TI provided API.
7-3RESERVEDR0hReserved
2-0VTRIM_DELTAR3hInternal. Only to be used through TI provided API.

12.4.1.42 MAC_BLE_0 Register (Offset = 2E8h) [Reset = 00000000h]

MAC_BLE_0 is shown in Figure 12-64 and described in Table 12-68.

Return to the Summary Table.

MAC BLE Address 0

Figure 12-64 MAC_BLE_0 Register
313029282726252423222120191817161514131211109876543210
ADDR_0_31
R-X
Table 12-68 MAC_BLE_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDR_0_31RXThe first 32-bits of the 64-bit MAC BLE address

Default value holds trim value from production test.

12.4.1.43 MAC_BLE_1 Register (Offset = 2ECh) [Reset = 00000000h]

MAC_BLE_1 is shown in Figure 12-65 and described in Table 12-69.

Return to the Summary Table.

MAC BLE Address 1

Figure 12-65 MAC_BLE_1 Register
313029282726252423222120191817161514131211109876543210
ADDR_32_63
R-X
Table 12-69 MAC_BLE_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDR_32_63RXThe last 32-bits of the 64-bit MAC BLE address

Default value holds trim value from production test.

12.4.1.44 MAC_15_4_0 Register (Offset = 2F0h) [Reset = 00000000h]

MAC_15_4_0 is shown in Figure 12-66 and described in Table 12-70.

Return to the Summary Table.

MAC IEEE 802.15.4 Address 0

Figure 12-66 MAC_15_4_0 Register
313029282726252423222120191817161514131211109876543210
ADDR_0_31
R-X
Table 12-70 MAC_15_4_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDR_0_31RXThe first 32-bits of the 64-bit MAC 15.4 address

Default value holds trim value from production test.

12.4.1.45 MAC_15_4_1 Register (Offset = 2F4h) [Reset = 00000000h]

MAC_15_4_1 is shown in Figure 12-67 and described in Table 12-71.

Return to the Summary Table.

MAC IEEE 802.15.4 Address 1

Figure 12-67 MAC_15_4_1 Register
313029282726252423222120191817161514131211109876543210
ADDR_32_63
R-X
Table 12-71 MAC_15_4_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDR_32_63RXThe last 32-bits of the 64-bit MAC 15.4 address

Default value holds trim value from production test.

12.4.1.46 FLASH_OTP_DATA4 Register (Offset = 308h) [Reset = 98989F9Fh]

FLASH_OTP_DATA4 is shown in Figure 12-68 and described in Table 12-72.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-68 FLASH_OTP_DATA4 Register
3130292827262524
STANDBY_MODE_SEL_INT_WRTSTANDBY_PW_SEL_INT_WRTDIS_STANDBY_INT_WRTDIS_IDLE_INT_WRTVIN_AT_X_INT_WRT
R-1hR-0hR-1hR-1hR-0h
2322212019181716
STANDBY_MODE_SEL_EXT_WRTSTANDBY_PW_SEL_EXT_WRTDIS_STANDBY_EXT_WRTDIS_IDLE_EXT_WRTVIN_AT_X_EXT_WRT
R-1hR-0hR-1hR-1hR-0h
15141312111098
STANDBY_MODE_SEL_INT_RDSTANDBY_PW_SEL_INT_RDDIS_STANDBY_INT_RDDIS_IDLE_INT_RDVIN_AT_X_INT_RD
R-1hR-0hR-1hR-1hR-7h
76543210
STANDBY_MODE_SEL_EXT_RDSTANDBY_PW_SEL_EXT_RDDIS_STANDBY_EXT_RDDIS_IDLE_EXT_RDVIN_AT_X_EXT_RD
R-1hR-0hR-1hR-1hR-7h
Table 12-72 FLASH_OTP_DATA4 Register Field Descriptions
BitFieldTypeResetDescription
31STANDBY_MODE_SEL_INT_WRTR1hInternal. Only to be used through TI provided API.
30-29STANDBY_PW_SEL_INT_WRTR0hInternal. Only to be used through TI provided API.
28DIS_STANDBY_INT_WRTR1hInternal. Only to be used through TI provided API.
27DIS_IDLE_INT_WRTR1hInternal. Only to be used through TI provided API.
26-24VIN_AT_X_INT_WRTR0hInternal. Only to be used through TI provided API.
23STANDBY_MODE_SEL_EXT_WRTR1hInternal. Only to be used through TI provided API.
22-21STANDBY_PW_SEL_EXT_WRTR0hInternal. Only to be used through TI provided API.
20DIS_STANDBY_EXT_WRTR1hInternal. Only to be used through TI provided API.
19DIS_IDLE_EXT_WRTR1hInternal. Only to be used through TI provided API.
18-16VIN_AT_X_EXT_WRTR0hInternal. Only to be used through TI provided API.
15STANDBY_MODE_SEL_INT_RDR1hInternal. Only to be used through TI provided API.
14-13STANDBY_PW_SEL_INT_RDR0hInternal. Only to be used through TI provided API.
12DIS_STANDBY_INT_RDR1hInternal. Only to be used through TI provided API.
11DIS_IDLE_INT_RDR1hInternal. Only to be used through TI provided API.
10-8VIN_AT_X_INT_RDR7hInternal. Only to be used through TI provided API.
7STANDBY_MODE_SEL_EXT_RDR1hInternal. Only to be used through TI provided API.
6-5STANDBY_PW_SEL_EXT_RDR0hInternal. Only to be used through TI provided API.
4DIS_STANDBY_EXT_RDR1hInternal. Only to be used through TI provided API.
3DIS_IDLE_EXT_RDR1hInternal. Only to be used through TI provided API.
2-0VIN_AT_X_EXT_RDR7hInternal. Only to be used through TI provided API.

12.4.1.47 MISC_TRIM Register (Offset = 30Ch) [Reset = FFFE003Bh]

MISC_TRIM is shown in Figure 12-69 and described in Table 12-73.

Return to the Summary Table.

Miscellaneous Trim Parameters

Figure 12-69 MISC_TRIM Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTRIM_RECHARGE_COMP_OFFSET
R-0hR-X
15141312111098
TRIM_RECHARGE_COMP_OFFSETTRIM_RECHARGE_COMP_REFLEVEL
R-XR-X
76543210
TEMPVSLOPE
R-3Bh
Table 12-73 MISC_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16-12TRIM_RECHARGE_COMP_OFFSETRXInternal. Only to be used through TI provided API.
11-8TRIM_RECHARGE_COMP_REFLEVELRXInternal. Only to be used through TI provided API.
7-0TEMPVSLOPER3BhSigned byte value representing the TEMP slope with battery voltage, in degrees C / V, with four fractional bits.

12.4.1.48 RCOSC_HF_TEMPCOMP Register (Offset = 310h) [Reset = 00000003h]

RCOSC_HF_TEMPCOMP is shown in Figure 12-70 and described in Table 12-74.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-70 RCOSC_HF_TEMPCOMP Register
31302928272625242322212019181716
FINE_RESISTORCTRIM
R-0hR-0h
1514131211109876543210
CTRIMFRACT_QUADCTRIMFRACT_SLOPE
R-0hR-3h
Table 12-74 RCOSC_HF_TEMPCOMP Register Field Descriptions
BitFieldTypeResetDescription
31-24FINE_RESISTORR0hInternal. Only to be used through TI provided API.
23-16CTRIMR0hInternal. Only to be used through TI provided API.
15-8CTRIMFRACT_QUADR0hInternal. Only to be used through TI provided API.
7-0CTRIMFRACT_SLOPER3hInternal. Only to be used through TI provided API.

12.4.1.49 ICEPICK_DEVICE_ID Register (Offset = 318h) [Reset = 3BB4102Fh]

ICEPICK_DEVICE_ID is shown in Figure 12-71 and described in Table 12-75.

Return to the Summary Table.

IcePick Device Identification
Reading this register and the FCFG1:USER_ID register is the only supported way of identifying a device.

Figure 12-71 ICEPICK_DEVICE_ID Register
31302928272625242322212019181716
PG_REVWAFER_ID
R-3hR-BB41h
1514131211109876543210
WAFER_IDMANUFACTURER_ID
R-BB41hR-2Fh
Table 12-75 ICEPICK_DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
31-28PG_REVR3hField used to distinguish revisions of the device.
27-12WAFER_IDRBB41hField used to identify silicon die.
11-0MANUFACTURER_IDR2FhManufacturer code.
0x02F: Texas Instruments

12.4.1.50 FCFG1_REVISION Register (Offset = 31Ch) [Reset = 0000002Ah]

FCFG1_REVISION is shown in Figure 12-72 and described in Table 12-76.

Return to the Summary Table.

Factory Configuration (FCFG1) Revision

Figure 12-72 FCFG1_REVISION Register
313029282726252423222120191817161514131211109876543210
REV
R-2Ah
Table 12-76 FCFG1_REVISION Register Field Descriptions
BitFieldTypeResetDescription
31-0REVR2AhThe revision number of the FCFG1 layout. This value will be read by application SW in order to determine which FCFG1 parameters that have valid values. This revision number must be incremented by 1 before any devices are to be produced if the FCFG1 layout has changed since the previous production of devices.
Value migth change without warning.

12.4.1.51 MISC_OTP_DATA Register (Offset = 320h) [Reset = 0000CFFFh]

MISC_OTP_DATA is shown in Figure 12-73 and described in Table 12-77.

Return to the Summary Table.

Misc OTP Data

Figure 12-73 MISC_OTP_DATA Register
3130292827262524
RCOSC_HF_ITUNERCOSC_HF_CRIM
R-XR-X
2322212019181716
RCOSC_HF_CRIMPER_M
R-XR-1h
15141312111098
PER_MPER_ERESERVED
R-1hR-4hR-0h
76543210
RESERVED
R-0h
Table 12-77 MISC_OTP_DATA Register Field Descriptions
BitFieldTypeResetDescription
31-28RCOSC_HF_ITUNERXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-20RCOSC_HF_CRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

19-15PER_MR1hInternal. Only to be used through TI provided API.
14-12PER_ER4hInternal. Only to be used through TI provided API.
11-0RESERVEDR0hReserved

12.4.1.52 IOCONF Register (Offset = 344h) [Reset = FFFFFF00h]

IOCONF is shown in Figure 12-74 and described in Table 12-78.

Return to the Summary Table.

IO Configuration

Figure 12-74 IOCONF Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDGPIO_CNT
R-0hR-X
Table 12-78 IOCONF Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0GPIO_CNTRXNumber of available DIOs.

Default value differs depending on partnumber.

12.4.1.53 CONFIG_IF_ADC Register (Offset = 34Ch) [Reset = 3460F400h]

CONFIG_IF_ADC is shown in Figure 12-75 and described in Table 12-79.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-75 CONFIG_IF_ADC Register
3130292827262524
FF2ADJFF3ADJ
R-3hR-4h
2322212019181716
INT3ADJFF1ADJ
R-6hR-0h
15141312111098
AAFCAPINT2ADJIFDIGLDO_TRIM_OUTPUT
R-3hR-DhR-X
76543210
IFDIGLDO_TRIM_OUTPUTIFANALDO_TRIM_OUTPUT
R-XR-X
Table 12-79 CONFIG_IF_ADC Register Field Descriptions
BitFieldTypeResetDescription
31-28FF2ADJR3hInternal. Only to be used through TI provided API.
27-24FF3ADJR4hInternal. Only to be used through TI provided API.
23-20INT3ADJR6hInternal. Only to be used through TI provided API.
19-16FF1ADJR0hInternal. Only to be used through TI provided API.
15-14AAFCAPR3hInternal. Only to be used through TI provided API.
13-10INT2ADJRDhInternal. Only to be used through TI provided API.
9-5IFDIGLDO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0IFANALDO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.54 CONFIG_OSC_TOP Register (Offset = 350h) [Reset = DC07FC00h]

CONFIG_OSC_TOP is shown in Figure 12-76 and described in Table 12-80.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-76 CONFIG_OSC_TOP Register
3130292827262524
RESERVEDXOSC_HF_ROW_Q12XOSC_HF_COLUMN_Q12
R-0hR-7hR-1FFh
2322212019181716
XOSC_HF_COLUMN_Q12
R-1FFh
15141312111098
XOSC_HF_COLUMN_Q12RCOSCLF_CTUNE_TRIM
R-1FFhR-X
76543210
RCOSCLF_CTUNE_TRIMRCOSCLF_RTUNE_TRIM
R-XR-0h
Table 12-80 CONFIG_OSC_TOP Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-26XOSC_HF_ROW_Q12R7hInternal. Only to be used through TI provided API.
25-10XOSC_HF_COLUMN_Q12R1FFhInternal. Only to be used through TI provided API.
9-2RCOSCLF_CTUNE_TRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

1-0RCOSCLF_RTUNE_TRIMR0hInternal. Only to be used through TI provided API.

12.4.1.55 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [Reset = 00000000h]

SOC_ADC_ABS_GAIN is shown in Figure 12-77 and described in Table 12-81.

Return to the Summary Table.

AUX_ADC Gain in Absolute Reference Mode

Figure 12-77 SOC_ADC_ABS_GAIN Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
SOC_ADC_ABS_GAIN_TEMP1
R-X
Table 12-81 SOC_ADC_ABS_GAIN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0SOC_ADC_ABS_GAIN_TEMP1RXSOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated in production test..

Default value holds log information from production test.

12.4.1.56 SOC_ADC_REL_GAIN Register (Offset = 360h) [Reset = 00000000h]

SOC_ADC_REL_GAIN is shown in Figure 12-78 and described in Table 12-82.

Return to the Summary Table.

AUX_ADC Gain in Relative Reference Mode

Figure 12-78 SOC_ADC_REL_GAIN Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
SOC_ADC_REL_GAIN_TEMP1
R-X
Table 12-82 SOC_ADC_REL_GAIN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0SOC_ADC_REL_GAIN_TEMP1RXSOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated in production test..

Default value holds trim value from production test.

12.4.1.57 SOC_ADC_OFFSET_INT Register (Offset = 368h) [Reset = 00000000h]

SOC_ADC_OFFSET_INT is shown in Figure 12-79 and described in Table 12-83.

Return to the Summary Table.

AUX_ADC Temperature Offsets in Absolute Reference Mode

Figure 12-79 SOC_ADC_OFFSET_INT Register
31302928272625242322212019181716
RESERVEDSOC_ADC_REL_OFFSET_TEMP1
R-0hR-X
1514131211109876543210
RESERVEDSOC_ADC_ABS_OFFSET_TEMP1
R-0hR-X
Table 12-83 SOC_ADC_OFFSET_INT Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16SOC_ADC_REL_OFFSET_TEMP1RXSOC_ADC offset in relative reference mode at temperature 1 (30C). Signed 8-bit number. Calculated in production test..

Default value holds trim value from production test.

15-8RESERVEDR0hReserved
7-0SOC_ADC_ABS_OFFSET_TEMP1RXSOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed 8-bit number. Calculated in production test..

Default value holds trim value from production test.

12.4.1.58 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [Reset = 0000C080h]

SOC_ADC_REF_TRIM_AND_OFFSET_EXT is shown in Figure 12-80 and described in Table 12-84.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-80 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSOC_ADC_REF_VOLTAGE_TRIM_TEMP1
R-0hR-X
Table 12-84 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0SOC_ADC_REF_VOLTAGE_TRIM_TEMP1RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.59 AMPCOMP_TH1 Register (Offset = 370h) [Reset = FF7B828Eh]

AMPCOMP_TH1 is shown in Figure 12-81 and described in Table 12-85.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-81 AMPCOMP_TH1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
HPMRAMP3_LTHRESERVED
R-1EhR-0h
15141312111098
HPMRAMP3_HTHIBIASCAP_LPTOHP_OL_CNT
R-20hR-Ah
76543210
IBIASCAP_LPTOHP_OL_CNTHPMRAMP1_TH
R-AhR-Eh
Table 12-85 AMPCOMP_TH1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-18HPMRAMP3_LTHR1EhInternal. Only to be used through TI provided API.
17-16RESERVEDR0hReserved
15-10HPMRAMP3_HTHR20hInternal. Only to be used through TI provided API.
9-6IBIASCAP_LPTOHP_OL_CNTRAhInternal. Only to be used through TI provided API.
5-0HPMRAMP1_THREhInternal. Only to be used through TI provided API.

12.4.1.60 AMPCOMP_TH2 Register (Offset = 374h) [Reset = 6B8B0303h]

AMPCOMP_TH2 is shown in Figure 12-82 and described in Table 12-86.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-82 AMPCOMP_TH2 Register
3130292827262524
LPMUPDATE_LTHRESERVED
R-1AhR-0h
2322212019181716
LPMUPDATE_HTMRESERVED
R-22hR-0h
15141312111098
ADC_COMP_AMPTH_LPMRESERVED
R-0hR-0h
76543210
ADC_COMP_AMPTH_HPMRESERVED
R-0hR-0h
Table 12-86 AMPCOMP_TH2 Register Field Descriptions
BitFieldTypeResetDescription
31-26LPMUPDATE_LTHR1AhInternal. Only to be used through TI provided API.
25-24RESERVEDR0hReserved
23-18LPMUPDATE_HTMR22hInternal. Only to be used through TI provided API.
17-16RESERVEDR0hReserved
15-10ADC_COMP_AMPTH_LPMR0hInternal. Only to be used through TI provided API.
9-8RESERVEDR0hReserved
7-2ADC_COMP_AMPTH_HPMR0hInternal. Only to be used through TI provided API.
1-0RESERVEDR0hReserved

12.4.1.61 AMPCOMP_CTRL1 Register (Offset = 378h) [Reset = FF483F47h]

AMPCOMP_CTRL1 is shown in Figure 12-83 and described in Table 12-87.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-83 AMPCOMP_CTRL1 Register
3130292827262524
RESERVEDAMPCOMP_REQ_MODERESERVED
R-0hR-1hR-0h
2322212019181716
IBIAS_OFFSETIBIAS_INIT
R-4hR-8h
15141312111098
LPM_IBIAS_WAIT_CNT_FINAL
R-3Fh
76543210
CAP_STEPIBIASCAP_HPTOLP_OL_CNT
R-4hR-7h
Table 12-87 AMPCOMP_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30AMPCOMP_REQ_MODER1hInternal. Only to be used through TI provided API.
29-24RESERVEDR0hReserved
23-20IBIAS_OFFSETR4hInternal. Only to be used through TI provided API.
19-16IBIAS_INITR8hInternal. Only to be used through TI provided API.
15-8LPM_IBIAS_WAIT_CNT_FINALR3FhInternal. Only to be used through TI provided API.
7-4CAP_STEPR4hInternal. Only to be used through TI provided API.
3-0IBIASCAP_HPTOLP_OL_CNTR7hInternal. Only to be used through TI provided API.

12.4.1.62 ANABYPASS_VALUE2 Register (Offset = 37Ch) [Reset = FFFFC3FFh]

ANABYPASS_VALUE2 is shown in Figure 12-84 and described in Table 12-88.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-84 ANABYPASS_VALUE2 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDXOSC_HF_IBIASTHERM
R-0hR-3FFh
Table 12-88 ANABYPASS_VALUE2 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-0XOSC_HF_IBIASTHERMR3FFhInternal. Only to be used through TI provided API.

12.4.1.63 VOLT_TRIM Register (Offset = 388h) [Reset = E0E0E0E0h]

VOLT_TRIM is shown in Figure 12-85 and described in Table 12-89.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-85 VOLT_TRIM Register
3130292827262524
RESERVEDVDDR_TRIM_HH
R-0hR-X
2322212019181716
RESERVEDVDDR_TRIM_H
R-0hR-X
15141312111098
RESERVEDVDDR_TRIM_SLEEP_H
R-0hR-X
76543210
RESERVEDTRIMBOD_H
R-0hR-X
Table 12-89 VOLT_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24VDDR_TRIM_HHRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-21RESERVEDR0hReserved
20-16VDDR_TRIM_HRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-13RESERVEDR0hReserved
12-8VDDR_TRIM_SLEEP_HRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

7-5RESERVEDR0hReserved
4-0TRIMBOD_HRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.64 OSC_CONF Register (Offset = 38Ch) [Reset = F00900E6h]

OSC_CONF is shown in Figure 12-86 and described in Table 12-90.

Return to the Summary Table.

OSC Configuration

Figure 12-86 OSC_CONF Register
3130292827262524
RESERVEDADC_SH_VBUF_ENADC_SH_MODE_ENATESTLF_RCOSCLF_IBIAS_TRIMXOSCLF_REGULATOR_TRIMXOSCLF_CMIRRWR_RATIO
R-0hR-1hR-1hR-0hR-0hR-0h
2322212019181716
XOSCLF_CMIRRWR_RATIOXOSC_HF_FAST_STARTXOSC_OPTIONHPOSC_OPTIONHPOSC_BIAS_HOLD_MODE_EN
R-0hR-1hR-XR-XR-1h
15141312111098
HPOSC_CURRMIRR_RATIOHPOSC_BIAS_RES_SET
R-XR-X
76543210
HPOSC_FILTER_ENHPOSC_BIAS_RECHARGE_DELAYRESERVEDHPOSC_SERIES_CAPHPOSC_DIV3_BYPASS
R-1hR-3hR-0hR-3hR-0h
Table 12-90 OSC_CONF Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29ADC_SH_VBUF_ENR1hTrim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN.
28ADC_SH_MODE_ENR1hTrim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN.
27ATESTLF_RCOSCLF_IBIAS_TRIMR0hTrim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM.
26-25XOSCLF_REGULATOR_TRIMR0hTrim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM.
24-21XOSCLF_CMIRRWR_RATIOR0hTrim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO.
20-19XOSC_HF_FAST_STARTR1hTrim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START.
18XOSC_OPTIONRX0: XOSC_HF unavailable (may not be bonded out)
1: XOSC_HF available (default)

Default value differs depending on partnumber.

17HPOSC_OPTIONRXInternal. Only to be used through TI provided API.

Default value differs depending on partnumber.

16HPOSC_BIAS_HOLD_MODE_ENR1hInternal. Only to be used through TI provided API.
15-12HPOSC_CURRMIRR_RATIORXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-8HPOSC_BIAS_RES_SETRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

7HPOSC_FILTER_ENR1hInternal. Only to be used through TI provided API.
6-5HPOSC_BIAS_RECHARGE_DELAYR3hInternal. Only to be used through TI provided API.
4-3RESERVEDR0hReserved
2-1HPOSC_SERIES_CAPR3hInternal. Only to be used through TI provided API.
0HPOSC_DIV3_BYPASSR0hInternal. Only to be used through TI provided API.

12.4.1.65 FREQ_OFFSET Register (Offset = 390h) [Reset = 00000000h]

FREQ_OFFSET is shown in Figure 12-87 and described in Table 12-91.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-87 FREQ_OFFSET Register
31302928272625242322212019181716
HPOSC_COMP_P0
R-X
1514131211109876543210
HPOSC_COMP_P1HPOSC_COMP_P2
R-XR-X
Table 12-91 FREQ_OFFSET Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_COMP_P0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-8HPOSC_COMP_P1RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

7-0HPOSC_COMP_P2RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.66 MISC_OTP_DATA_1 Register (Offset = 398h) [Reset = E08403F8h]

MISC_OTP_DATA_1 is shown in Figure 12-88 and described in Table 12-92.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-88 MISC_OTP_DATA_1 Register
3130292827262524
RESERVEDPEAK_DET_ITRIMHP_BUF_ITRIM
R-0hR-0hR-0h
2322212019181716
LP_BUF_ITRIMDBLR_LOOP_FILTER_RESET_VOLTAGEHPM_IBIAS_WAIT_CNT
R-2hR-0hR-100h
15141312111098
HPM_IBIAS_WAIT_CNTLPM_IBIAS_WAIT_CNT
R-100hR-3Fh
76543210
LPM_IBIAS_WAIT_CNTIDAC_STEP
R-3FhR-8h
Table 12-92 MISC_OTP_DATA_1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-27PEAK_DET_ITRIMR0hInternal. Only to be used through TI provided API.
26-24HP_BUF_ITRIMR0hInternal. Only to be used through TI provided API.
23-22LP_BUF_ITRIMR2hInternal. Only to be used through TI provided API.
21-20DBLR_LOOP_FILTER_RESET_VOLTAGER0hInternal. Only to be used through TI provided API.
19-10HPM_IBIAS_WAIT_CNTR100hInternal. Only to be used through TI provided API.
9-4LPM_IBIAS_WAIT_CNTR3FhInternal. Only to be used through TI provided API.
3-0IDAC_STEPR8hInternal. Only to be used through TI provided API.

12.4.1.67 SHDW_DIE_ID_0 Register (Offset = 3D0h) [Reset = 00000000h]

SHDW_DIE_ID_0 is shown in Figure 12-89 and described in Table 12-93.

Return to the Summary Table.

Shadow of DIE_ID_0 register in eFuse

Figure 12-89 SHDW_DIE_ID_0 Register
313029282726252423222120191817161514131211109876543210
ID_31_0
R-X
Table 12-93 SHDW_DIE_ID_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_31_0RXShadow of DIE_ID_0 register in eFuse row number 5

Default value depends on eFuse value.

12.4.1.68 SHDW_DIE_ID_1 Register (Offset = 3D4h) [Reset = 00000000h]

SHDW_DIE_ID_1 is shown in Figure 12-90 and described in Table 12-94.

Return to the Summary Table.

Shadow of DIE_ID_1 register in eFuse

Figure 12-90 SHDW_DIE_ID_1 Register
313029282726252423222120191817161514131211109876543210
ID_63_32
R-X
Table 12-94 SHDW_DIE_ID_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_63_32RXShadow of DIE_ID_1 register in eFuse row number 6

Default value depends on eFuse value.

12.4.1.69 SHDW_DIE_ID_2 Register (Offset = 3D8h) [Reset = 00000000h]

SHDW_DIE_ID_2 is shown in Figure 12-91 and described in Table 12-95.

Return to the Summary Table.

Shadow of DIE_ID_2 register in eFuse

Figure 12-91 SHDW_DIE_ID_2 Register
313029282726252423222120191817161514131211109876543210
ID_95_64
R-X
Table 12-95 SHDW_DIE_ID_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_95_64RXShadow of DIE_ID_2 register in eFuse row number 7

Default value depends on eFuse value.

12.4.1.70 SHDW_DIE_ID_3 Register (Offset = 3DCh) [Reset = 00000000h]

SHDW_DIE_ID_3 is shown in Figure 12-92 and described in Table 12-96.

Return to the Summary Table.

Shadow of DIE_ID_3 register in eFuse

Figure 12-92 SHDW_DIE_ID_3 Register
313029282726252423222120191817161514131211109876543210
ID_127_96
R-X
Table 12-96 SHDW_DIE_ID_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_127_96RXShadow of DIE_ID_3 register in eFuse row number 8

Default value depends on eFuse value.

12.4.1.71 SHDW_OSC_BIAS_LDO_TRIM Register (Offset = 3F8h) [Reset = 00000000h]

SHDW_OSC_BIAS_LDO_TRIM is shown in Figure 12-93 and described in Table 12-97.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-93 SHDW_OSC_BIAS_LDO_TRIM Register
3130292827262524
RESERVEDTRIMMAG
R-0hR-X
2322212019181716
TRIMMAGTRIMIREFITRIM_DIG_LDO
R-XR-XR-X
15141312111098
VTRIM_DIGVTRIM_COARSE
R-XR-X
76543210
RCOSCHF_CTRIM
R-X
Table 12-97 SHDW_OSC_BIAS_LDO_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR0hReserved
26-23TRIMMAGRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

22-18TRIMIREFRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

17-16ITRIM_DIG_LDORXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

15-12VTRIM_DIGRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

11-8VTRIM_COARSERXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

7-0RCOSCHF_CTRIMRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

12.4.1.72 SHDW_ANA_TRIM Register (Offset = 3FCh) [Reset = 00000000h]

SHDW_ANA_TRIM is shown in Figure 12-94 and described in Table 12-98.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-94 SHDW_ANA_TRIM Register
3130292827262524
RESERVEDALT_VDDR_TRIMDET_LOGIC_DISBOD_BANDGAP_TRIM_CNF_EXTBOD_BANDGAP_TRIM_CNFVDDR_ENABLE_PG1
R-0hR-XR-XR-XR-XR-X
2322212019181716
VDDR_OK_HYSIPTAT_TRIMVDDR_TRIM
R-XR-XR-X
15141312111098
TRIMBOD_INTMODETRIMBOD_EXTMODE
R-XR-X
76543210
TRIMBOD_EXTMODETRIMTEMP
R-XR-X
Table 12-98 SHDW_ANA_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ALT_VDDR_TRIMRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

29DET_LOGIC_DISRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

28-27BOD_BANDGAP_TRIM_CNF_EXTRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

26-25BOD_BANDGAP_TRIM_CNFRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

24VDDR_ENABLE_PG1RXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

23VDDR_OK_HYSRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

22-21IPTAT_TRIMRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

20-16VDDR_TRIMRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

15-11TRIMBOD_INTMODERXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

10-6TRIMBOD_EXTMODERXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

5-0TRIMTEMPRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

12.4.1.73 OSC_CONF1 Register (Offset = 408h) [Reset = FFFF0000h]

OSC_CONF1 is shown in Figure 12-95 and described in Table 12-99.

Return to the Summary Table.

Oscillator configuration

Figure 12-95 OSC_CONF1 Register
3130292827262524
RCOSC_MF_BIAS_HTEMPRCOSC_MF_TEMP_DEPEND_MODERCOSC_MF_SINGLE_TRIM_METHODRESERVED
R-XR-XR-XR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRCOSC_MF_BIAS_ADJ
R-0hR-X
Table 12-99 OSC_CONF1 Register Field Descriptions
BitFieldTypeResetDescription
31-28RCOSC_MF_BIAS_HTEMPRXInternal. Only to be used through TI provided API.
27RCOSC_MF_TEMP_DEPEND_MODERXInternal. Only to be used through TI provided API.
26RCOSC_MF_SINGLE_TRIM_METHODRXInternal. Only to be used through TI provided API.
25-4RESERVEDR0hReserved
3-0RCOSC_MF_BIAS_ADJRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.74 DAC_BIAS_CNF Register (Offset = 40Ch) [Reset = FFFC00FFh]

DAC_BIAS_CNF is shown in Figure 12-96 and described in Table 12-100.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-96 DAC_BIAS_CNF Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDLPM_TRIM_IOUT
R-0hR-X
15141312111098
LPM_TRIM_IOUTLPM_BIAS_WIDTH_TRIMLPM_BIAS_BACKUP_EN
R-XR-0hR-0h
76543210
RESERVED
R-0h
Table 12-100 DAC_BIAS_CNF Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-12LPM_TRIM_IOUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-9LPM_BIAS_WIDTH_TRIMR0hInternal. Only to be used through TI provided API.
8LPM_BIAS_BACKUP_ENR0hInternal. Only to be used through TI provided API.
7-0RESERVEDR0hReserved

12.4.1.75 TFW_PROBE Register (Offset = 418h) [Reset = 00000000h]

TFW_PROBE is shown in Figure 12-97 and described in Table 12-101.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-97 TFW_PROBE Register
313029282726252423222120191817161514131211109876543210
REV
R-X
Table 12-101 TFW_PROBE Register Field Descriptions
BitFieldTypeResetDescription
31-0REVRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.76 TFW_FT Register (Offset = 41Ch) [Reset = 00000000h]

TFW_FT is shown in Figure 12-98 and described in Table 12-102.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-98 TFW_FT Register
313029282726252423222120191817161514131211109876543210
REV
R-X
Table 12-102 TFW_FT Register Field Descriptions
BitFieldTypeResetDescription
31-0REVRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.77 DAC_CAL0 Register (Offset = 420h) [Reset = 00000000h]

DAC_CAL0 is shown in Figure 12-99 and described in Table 12-103.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-99 DAC_CAL0 Register
31302928272625242322212019181716
SOC_DAC_VOUT_CAL_DECOUPLE_C2
R-X
1514131211109876543210
SOC_DAC_VOUT_CAL_DECOUPLE_C1
R-X
Table 12-103 DAC_CAL0 Register Field Descriptions
BitFieldTypeResetDescription
31-16SOC_DAC_VOUT_CAL_DECOUPLE_C2RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-0SOC_DAC_VOUT_CAL_DECOUPLE_C1RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.78 DAC_CAL1 Register (Offset = 424h) [Reset = 00000000h]

DAC_CAL1 is shown in Figure 12-100 and described in Table 12-104.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-100 DAC_CAL1 Register
31302928272625242322212019181716
SOC_DAC_VOUT_CAL_PRECH_C2
R-X
1514131211109876543210
SOC_DAC_VOUT_CAL_PRECH_C1
R-X
Table 12-104 DAC_CAL1 Register Field Descriptions
BitFieldTypeResetDescription
31-16SOC_DAC_VOUT_CAL_PRECH_C2RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-0SOC_DAC_VOUT_CAL_PRECH_C1RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.79 DAC_CAL2 Register (Offset = 428h) [Reset = 00000000h]

DAC_CAL2 is shown in Figure 12-101 and described in Table 12-105.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-101 DAC_CAL2 Register
31302928272625242322212019181716
SOC_DAC_VOUT_CAL_ADCREF_C2
R-X
1514131211109876543210
SOC_DAC_VOUT_CAL_ADCREF_C1
R-X
Table 12-105 DAC_CAL2 Register Field Descriptions
BitFieldTypeResetDescription
31-16SOC_DAC_VOUT_CAL_ADCREF_C2RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-0SOC_DAC_VOUT_CAL_ADCREF_C1RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12.4.1.80 DAC_CAL3 Register (Offset = 42Ch) [Reset = 00000000h]

DAC_CAL3 is shown in Figure 12-102 and described in Table 12-106.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-102 DAC_CAL3 Register
31302928272625242322212019181716
SOC_DAC_VOUT_CAL_VDDS_C2
R-X
1514131211109876543210
SOC_DAC_VOUT_CAL_VDDS_C1
R-X
Table 12-106 DAC_CAL3 Register Field Descriptions
BitFieldTypeResetDescription
31-16SOC_DAC_VOUT_CAL_VDDS_C2RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-0SOC_DAC_VOUT_CAL_VDDS_C1RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.