SWCU185G January   2018  – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  3. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4F
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Sensor Controller
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  4. 3 Arm® Cortex®-M4F Processor
    1. 3.1 Arm® Cortex®-M4F Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Floating Point Unit (FPU)
      5. 3.3.5 Memory Protection Unit (MPU)
      6. 3.3.6 Arm® Cortex®-M4F System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4F Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4F Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Floating Point Unit (FPU)
      1. 3.7.1 About the FPU
      2. 3.7.2 FPU Functional Description
        1. 3.7.2.1 FPU Views of the Register Bank
        2. 3.7.2.2 Modes of Operation
          1. 3.7.2.2.1 Full-Compliance Mode
          2. 3.7.2.2.2 Flush-to-Zero Mode
          3. 3.7.2.2.3 Default NaN Mode
        3. 3.7.2.3 FPU Instruction Set
        4. 3.7.2.4 Compliance With the IEEE 754 Standard
        5. 3.7.2.5 Complete Implementation of the IEEE 754 Standard
        6. 3.7.2.6 IEEE 754 Standard Implementation Choices
          1. 3.7.2.6.1 NaN Handling
          2. 3.7.2.6.2 Comparisons
          3. 3.7.2.6.3 Underflow
        7. 3.7.2.7 Exceptions
      3. 3.7.3 FPU Programmers Model
        1. 3.7.3.1 Enabling the FPU
          1. 3.7.3.1.1 Enabling the FPU
    8. 3.8 Memory Protection Unit (MPU)
      1. 3.8.1 About the MPU
      2. 3.8.2 MPU Functional Description
      3. 3.8.3 MPU Programmers Model
    9. 3.9 Arm® Cortex®-M4F Processor Registers
      1. 3.9.1 CPU_DWT Registers
      2. 3.9.2 CPU_FPB Registers
      3. 3.9.3 CPU_ITM Registers
      4. 3.9.4 CPU_SCS Registers
      5. 3.9.5 CPU_TPIU Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Arm® Cortex®-M4F Peripherals
    1. 5.1 Arm® Cortex®-M4F Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  7. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  8. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  9. 8 Power, Reset, and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 DDI_0_OSC Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  10. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  11. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM_MMR Registers
      2. 10.7.2 SRAM Registers
  12. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  13. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  14. 13Cryptography
    1. 13.1 AES and Hash Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master PROT Enable
          1. 13.5.4.2.1 Master PROT-Privileged Access-Enable
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
        5. 13.5.6.5 Hash Engine
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Hashing
        1. 13.7.3.1 Data Format and Byte Order
        2. 13.7.3.2 Basic Hash With Data From DMA
          1. 13.7.3.2.1 New Hash Session With Digest Read Through Slave
          2. 13.7.3.2.2 New Hash Session With Digest to External Memory
          3. 13.7.3.2.3 Resumed Hash Session
        3. 13.7.3.3 HMAC
          1. 13.7.3.3.1 Secure HMAC
        4. 13.7.3.4 Alternative Basic Hash Where Data Originates From Slave Interface
          1. 13.7.3.4.1 New Hash Session
          2. 13.7.3.4.2 Resumed Hash Session
      4. 13.7.4 Encryption and Decryption
        1. 13.7.4.1 Data Format and Byte Order
        2. 13.7.4.2 Key Store
          1. 13.7.4.2.1 Load Keys From External Memory
        3. 13.7.4.3 Basic AES Modes
          1. 13.7.4.3.1 AES-ECB
          2. 13.7.4.3.2 AES-CBC
          3. 13.7.4.3.3 AES-CTR
          4. 13.7.4.3.4 Programming Sequence With DMA Data
        4. 13.7.4.4 CBC-MAC
          1. 13.7.4.4.1 Programming Sequence for CBC-MAC
        5. 13.7.4.5 AES-CCM
          1. 13.7.4.5.1 Programming Sequence for AES-CCM
        6. 13.7.4.6 AES-GCM
          1. 13.7.4.6.1 Programming Sequence for AES-GCM
      5. 13.7.5 Exceptions Handling
        1. 13.7.5.1 Soft Reset
        2. 13.7.5.2 External Port Errors
        3. 13.7.5.3 Key Store Errors
          1. 13.7.5.3.1 PKA Engine
          2. 13.7.5.3.2 Functional Description
            1. 13.7.5.3.2.1 Module Architecture
          3. 13.7.5.3.3 PKA RAM
            1. 13.7.5.3.3.1 PKCP Operations
            2. 13.7.5.3.3.2 Sequencer Operations
              1. 13.7.5.3.3.2.1 Modular Exponentiation Operations
              2. 13.7.5.3.3.2.2 Modular Inversion Operation
              3. 13.7.5.3.3.2.3 Performance
              4. 13.7.5.3.3.2.4 ECC Operations
              5. 13.7.5.3.3.2.5 Performance
              6. 13.7.5.3.3.2.6 ExpMod Performance
              7. 13.7.5.3.3.2.7 Modular Inversion Performance
              8. 13.7.5.3.3.2.8 ECC Operation Performance
            3. 13.7.5.3.3.3 Sequencer ROM Behavior and Interfaces
            4. 13.7.5.3.3.4 Register Configurations
            5. 13.7.5.3.3.5 Operation Sequence
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  15. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 UDMA Registers
  17. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  18. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  19. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  20. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 AIODIO
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 SMPH
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPIM
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
              1. 20.4.7.2.5.1.1 Timer Period and Pulse Width Capture
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.2.1 Center-Aligned PWM Generation by Channel 0
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.3.1 Edge-Aligned PWM Generation by Channel 0
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 COMPA
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 COMPB
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference DAC
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 ISRC
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  24. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

8.8.1 DDI_0_OSC Registers

Table 8-8 lists the memory-mapped registers for the DDI_0_OSC registers. All register offset addresses not listed in Table 8-8 should be considered as reserved locations and the register contents should not be modified.

Table 8-8 DDI_0_OSC Registers
OffsetAcronymRegister NameSection
0hCTL0Control 0CTL0 Register (Offset = 0h) [Reset = 00000000h]
4hCTL1Control 1CTL1 Register (Offset = 4h) [Reset = 00000000h]
8hRADCEXTCFGRADC External ConfigurationRADCEXTCFG Register (Offset = 8h) [Reset = 00000000h]
ChAMPCOMPCTLAmplitude Compensation ControlAMPCOMPCTL Register (Offset = Ch) [Reset = 00000000h]
10hAMPCOMPTH1Amplitude Compensation Threshold 1AMPCOMPTH1 Register (Offset = 10h) [Reset = 00000000h]
14hAMPCOMPTH2Amplitude Compensation Threshold 2AMPCOMPTH2 Register (Offset = 14h) [Reset = 00000000h]
18hANABYPASSVAL1Analog Bypass Values 1ANABYPASSVAL1 Register (Offset = 18h) [Reset = 00000000h]
1ChANABYPASSVAL2InternalANABYPASSVAL2 Register (Offset = 1Ch) [Reset = 00000000h]
20hATESTCTLAnalog Test ControlATESTCTL Register (Offset = 20h) [Reset = 00000000h]
24hADCDOUBLERNANOAMPCTLADC Doubler Nanoamp ControlADCDOUBLERNANOAMPCTL Register (Offset = 24h) [Reset = 00000000h]
28hXOSCHFCTLXOSCHF ControlXOSCHFCTL Register (Offset = 28h) [Reset = 00000000h]
2ChLFOSCCTLLow Frequency Oscillator ControlLFOSCCTL Register (Offset = 2Ch) [Reset = 00000000h]
30hRCOSCHFCTLRCOSCHF ControlRCOSCHFCTL Register (Offset = 30h) [Reset = 00000000h]
34hRCOSCMFCTLRCOSC_MF ControlRCOSCMFCTL Register (Offset = 34h) [Reset = 00000000h]
3ChSTAT0Status 0STAT0 Register (Offset = 3Ch) [Reset = 00000000h]
40hSTAT1Status 1STAT1 Register (Offset = 40h) [Reset = 00000000h]
44hSTAT2Status 2STAT2 Register (Offset = 44h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Table 8-9 shows the codes that are used for access types in this section.

Table 8-9 DDI_0_OSC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.8.1.1 CTL0 Register (Offset = 0h) [Reset = 00000000h]

CTL0 is shown in Figure 8-7 and described in Table 8-10.

Return to the Summary Table.

Control 0
Controls clock source selects

Figure 8-7 CTL0 Register
3130292827262524
XTAL_IS_24MRESERVEDBYPASS_XOSC_LF_CLK_QUALBYPASS_RCOSC_LF_CLK_QUALDOUBLER_START_DURATIONDOUBLER_RESET_DURATIONCLK_DCDC_SRC_SEL
R/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDHPOSC_MODE_ENRESERVEDRCOSC_LF_TRIMMEDXOSC_HF_POWER_MODEXOSC_LF_DIG_BYPASSCLK_LOSS_ENACLK_TDC_SRC_SEL
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ACLK_TDC_SRC_SELACLK_REF_SRC_SELSCLK_LF_SRC_SELRESERVEDSCLK_HF_SRC_SEL
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 8-10 CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31XTAL_IS_24MR/W0hSet based on the accurate high frequency XTAL.
30RESERVEDR0hReserved
29BYPASS_XOSC_LF_CLK_QUALR/W0hInternal. Only to be used through TI provided API.
28BYPASS_RCOSC_LF_CLK_QUALR/W0hInternal. Only to be used through TI provided API.
27-26DOUBLER_START_DURATIONR/W0hInternal. Only to be used through TI provided API.
25DOUBLER_RESET_DURATIONR/W0hInternal. Only to be used through TI provided API.
24CLK_DCDC_SRC_SELR/W0hSelect DCDC clock source.
0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC
1: CLK_DCDC is always 48 MHz clock from RCOSC
23-15RESERVEDR0hReserved
14HPOSC_MODE_ENR/W0h0: HPOSC mode is not enabled. The 48 MHz crystal is required for radio operation.
1: Enables HPOSC mode. The internal HPOSC can be used as HF system clock and for radio operation.
13RESERVEDR0hReserved
12RCOSC_LF_TRIMMEDR/W0hInternal. Only to be used through TI provided API.
11XOSC_HF_POWER_MODER/W0hInternal. Only to be used through TI provided API.
10XOSC_LF_DIG_BYPASSR/W0hBypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock.
0: Use 32kHz XOSC as xosc_lf clock source
1: Use digital input (from AON) as xosc_lf clock source.
This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf as the sclk_lf source. The muxing performed by this bit is not glitch free. The following procedure must be followed when changing this field to avoid glitches on sclk_lf.
1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock source.
2) Set or clear this bit to bypass or not bypass the xosc_lf.
3) Set SCLK_LF_SRC_SEL to use xosc_lf.
It is recommended that either the rcosc_hf or xosc_hf (whichever is currently active) be selected as the source in step 1 above. This provides a faster clock change.
9CLK_LOSS_ENR/W0hEnable clock loss detection and hence the indicators to the system controller. Checks both SCLK_HF, SCLK_MF and SCLK_LF clock loss indicators.
0: Disable
1: Enable
Clock loss detection must be disabled when changing the sclk_lf source. STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf source has completed.
8-7ACLK_TDC_SRC_SELR/W0hSource select for aclk_tdc.
00: RCOSC_HF (48MHz)
01: RCOSC_HF (24MHz)
10: XOSC_HF (24MHz)
11: Not used
6-4ACLK_REF_SRC_SELR/W0hSource select for aclk_ref
000: RCOSC_HF derived (31.25kHz)
001: XOSC_HF derived (31.25kHz)
010: RCOSC_LF (32kHz)
011: XOSC_LF (32.768kHz)
100: RCOSC_MF (2MHz)
101-111: Not used
3-2SCLK_LF_SRC_SELR/W0hSource select for sclk_lf
0h = Low frequency clock derived from High Frequency RCOSC
1h = Low frequency clock derived from High Frequency XOSC or HPOSC clk (use HPOSC when HPOSC_MODE_EN = 1)
2h = Low frequency RCOSC
3h = Low frequency XOSC
1RESERVEDR0hReserved
0SCLK_HF_SRC_SELR/W0hSource select for sclk_hf.
0h = High frequency RCOSC clock
1h = High frequency XOSC or HPOSC clk (use HPOSC when HPOSC_MODE_EN = 1

8.8.1.2 CTL1 Register (Offset = 4h) [Reset = 00000000h]

CTL1 is shown in Figure 8-8 and described in Table 8-11.

Return to the Summary Table.

Control 1
This register contains OSC_DIG configuration

Figure 8-8 CTL1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRCOSCHFCTRIMFRACTRCOSCHFCTRIMFRACT_ENRESERVED
R-0hR/W-0hR/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDXOSC_HF_FAST_START
R-0hR/W-0h
Table 8-11 CTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved
22-18RCOSCHFCTRIMFRACTR/W0hInternal. Only to be used through TI provided API.
17RCOSCHFCTRIMFRACT_ENR/W0hInternal. Only to be used through TI provided API.
16-2RESERVEDR0hReserved
1-0XOSC_HF_FAST_STARTR/W0hInternal. Only to be used through TI provided API.

8.8.1.3 RADCEXTCFG Register (Offset = 8h) [Reset = 00000000h]

RADCEXTCFG is shown in Figure 8-9 and described in Table 8-12.

Return to the Summary Table.

RADC External Configuration

Figure 8-9 RADCEXTCFG Register
3130292827262524
HPM_IBIAS_WAIT_CNT
R/W-0h
2322212019181716
HPM_IBIAS_WAIT_CNTLPM_IBIAS_WAIT_CNT
R/W-0hR/W-0h
15141312111098
IDAC_STEPRADC_DAC_TH
R/W-0hR/W-0h
76543210
RADC_DAC_THRADC_MODE_IS_SARRESERVED
R/W-0hR/W-0hR-0h
Table 8-12 RADCEXTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-22HPM_IBIAS_WAIT_CNTR/W0hInternal. Only to be used through TI provided API.
21-16LPM_IBIAS_WAIT_CNTR/W0hInternal. Only to be used through TI provided API.
15-12IDAC_STEPR/W0hInternal. Only to be used through TI provided API.
11-6RADC_DAC_THR/W0hInternal. Only to be used through TI provided API.
5RADC_MODE_IS_SARR/W0hInternal. Only to be used through TI provided API.
4-0RESERVEDR0hReserved

8.8.1.4 AMPCOMPCTL Register (Offset = Ch) [Reset = 00000000h]

AMPCOMPCTL is shown in Figure 8-10 and described in Table 8-13.

Return to the Summary Table.

Amplitude Compensation Control

Figure 8-10 AMPCOMPCTL Register
3130292827262524
RESERVEDAMPCOMP_REQ_MODEAMPCOMP_FSM_UPDATE_RATEAMPCOMP_SW_CTRLAMPCOMP_SW_ENRESERVED
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
2322212019181716
IBIAS_OFFSETIBIAS_INIT
R/W-0hR/W-0h
15141312111098
LPM_IBIAS_WAIT_CNT_FINAL
R/W-0h
76543210
CAP_STEPIBIASCAP_HPTOLP_OL_CNT
R/W-0hR/W-0h
Table 8-13 AMPCOMPCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30AMPCOMP_REQ_MODER/W0hInternal. Only to be used through TI provided API.
29-28AMPCOMP_FSM_UPDATE_RATER/W0hInternal. Only to be used through TI provided API.
27AMPCOMP_SW_CTRLR/W0hInternal. Only to be used through TI provided API.
26AMPCOMP_SW_ENR/W0hInternal. Only to be used through TI provided API.
25-24RESERVEDR0hReserved
23-20IBIAS_OFFSETR/W0hInternal. Only to be used through TI provided API.
19-16IBIAS_INITR/W0hInternal. Only to be used through TI provided API.
15-8LPM_IBIAS_WAIT_CNT_FINALR/W0hInternal. Only to be used through TI provided API.
7-4CAP_STEPR/W0hInternal. Only to be used through TI provided API.
3-0IBIASCAP_HPTOLP_OL_CNTR/W0hInternal. Only to be used through TI provided API.

8.8.1.5 AMPCOMPTH1 Register (Offset = 10h) [Reset = 00000000h]

AMPCOMPTH1 is shown in Figure 8-11 and described in Table 8-14.

Return to the Summary Table.

Amplitude Compensation Threshold 1
This register contains threshold values for amplitude compensation algorithm

Figure 8-11 AMPCOMPTH1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
HPMRAMP3_LTHRESERVED
R/W-0hR-0h
15141312111098
HPMRAMP3_HTHIBIASCAP_LPTOHP_OL_CNT
R/W-0hR/W-0h
76543210
IBIASCAP_LPTOHP_OL_CNTHPMRAMP1_TH
R/W-0hR/W-0h
Table 8-14 AMPCOMPTH1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-18HPMRAMP3_LTHR/W0hInternal. Only to be used through TI provided API.
17-16RESERVEDR0hReserved
15-10HPMRAMP3_HTHR/W0hInternal. Only to be used through TI provided API.
9-6IBIASCAP_LPTOHP_OL_CNTR/W0hInternal. Only to be used through TI provided API.
5-0HPMRAMP1_THR/W0hInternal. Only to be used through TI provided API.

8.8.1.6 AMPCOMPTH2 Register (Offset = 14h) [Reset = 00000000h]

AMPCOMPTH2 is shown in Figure 8-12 and described in Table 8-15.

Return to the Summary Table.

Amplitude Compensation Threshold 2
This register contains threshold values for amplitude compensation algorithm.

Figure 8-12 AMPCOMPTH2 Register
3130292827262524
LPMUPDATE_LTHRESERVED
R/W-0hR-0h
2322212019181716
LPMUPDATE_HTHRESERVED
R/W-0hR-0h
15141312111098
ADC_COMP_AMPTH_LPMRESERVED
R/W-0hR-0h
76543210
ADC_COMP_AMPTH_HPMRESERVED
R/W-0hR-0h
Table 8-15 AMPCOMPTH2 Register Field Descriptions
BitFieldTypeResetDescription
31-26LPMUPDATE_LTHR/W0hInternal. Only to be used through TI provided API.
25-24RESERVEDR0hReserved
23-18LPMUPDATE_HTHR/W0hInternal. Only to be used through TI provided API.
17-16RESERVEDR0hReserved
15-10ADC_COMP_AMPTH_LPMR/W0hInternal. Only to be used through TI provided API.
9-8RESERVEDR0hReserved
7-2ADC_COMP_AMPTH_HPMR/W0hInternal. Only to be used through TI provided API.
1-0RESERVEDR0hReserved

8.8.1.7 ANABYPASSVAL1 Register (Offset = 18h) [Reset = 00000000h]

ANABYPASSVAL1 is shown in Figure 8-13 and described in Table 8-16.

Return to the Summary Table.

Analog Bypass Values 1

Figure 8-13 ANABYPASSVAL1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDXOSC_HF_ROW_Q12
R-0hR/W-0h
15141312111098
XOSC_HF_COLUMN_Q12
R/W-0h
76543210
XOSC_HF_COLUMN_Q12
R/W-0h
Table 8-16 ANABYPASSVAL1 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16XOSC_HF_ROW_Q12R/W0hInternal. Only to be used through TI provided API.
15-0XOSC_HF_COLUMN_Q12R/W0hInternal. Only to be used through TI provided API.

8.8.1.8 ANABYPASSVAL2 Register (Offset = 1Ch) [Reset = 00000000h]

ANABYPASSVAL2 is shown in Figure 8-14 and described in Table 8-17.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 8-14 ANABYPASSVAL2 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDXOSC_HF_IBIASTHERM
R-0hR/W-0h
Table 8-17 ANABYPASSVAL2 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-0XOSC_HF_IBIASTHERMR/W0hInternal. Only to be used through TI provided API.

8.8.1.9 ATESTCTL Register (Offset = 20h) [Reset = 00000000h]

ATESTCTL is shown in Figure 8-15 and described in Table 8-18.

Return to the Summary Table.

Analog Test Control

Figure 8-15 ATESTCTL Register
3130292827262524
SCLK_LF_AUX_ENRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
TEST_RCOSCMFATEST_RCOSCMFRESERVED
R/W-0hR/W-0hR-0h
76543210
RESERVED
R-0h
Table 8-18 ATESTCTL Register Field Descriptions
BitFieldTypeResetDescription
31SCLK_LF_AUX_ENR/W0hEnable 32 kHz clock to AUX_COMPB.
30-16RESERVEDR0hReserved
15-14TEST_RCOSCMFR/W0hTest mode control for RCOSC_MF
0x0: test modes disabled
0x1: boosted bias current into self biased inverter
0x2: clock qualification disabled
0x3: boosted bias current into self biased inverter + clock qualification disabled
13-12ATEST_RCOSCMFR/W0hATEST control for RCOSC_MF
0x0: ATEST disabled
0x1: ATEST enabled, VDD_LOCAL connected, ATEST internal to **RCOSC_MF* enabled to send out 2MHz clock.
0x2: ATEST disabled
0x3: ATEST enabled, bias current connected, ATEST internal to **RCOSC_MF* enabled to send out 2MHz clock.
11-0RESERVEDR0hReserved

8.8.1.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [Reset = 00000000h]

ADCDOUBLERNANOAMPCTL is shown in Figure 8-16 and described in Table 8-19.

Return to the Summary Table.

ADC Doubler Nanoamp Control

Figure 8-16 ADCDOUBLERNANOAMPCTL Register
3130292827262524
RESERVEDNANOAMP_BIAS_ENABLE
R-0hR/W-0h
2322212019181716
SPARE23RESERVED
R/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDADC_SH_MODE_ENADC_SH_VBUF_ENRESERVEDADC_IREF_CTRL
R-0hR/W-0hR/W-0hR-0hR/W-0h
Table 8-19 ADCDOUBLERNANOAMPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24NANOAMP_BIAS_ENABLER/W0hInternal. Only to be used through TI provided API.
23SPARE23R/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
22-6RESERVEDR0hReserved
5ADC_SH_MODE_ENR/W0hInternal. Only to be used through TI provided API.
4ADC_SH_VBUF_ENR/W0hInternal. Only to be used through TI provided API.
3-2RESERVEDR0hReserved
1-0ADC_IREF_CTRLR/W0hInternal. Only to be used through TI provided API.

8.8.1.11 XOSCHFCTL Register (Offset = 28h) [Reset = 00000000h]

XOSCHFCTL is shown in Figure 8-17 and described in Table 8-20.

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XOSCHF Control

Figure 8-17 XOSCHFCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTCXO_MODE_XOSC_HF_ENTCXO_MODERESERVEDPEAK_DET_ITRIM
R-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
RESERVEDBYPASSRESERVEDHP_BUF_ITRIMLP_BUF_ITRIM
R-0hR/W-0hR-0hR/W-0hR/W-0h
Table 8-20 XOSCHFCTL Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13TCXO_MODE_XOSC_HF_ENR/W0hIf this register is 1 when TCXO_MODE is 1, then the XOSC_HF is enabled, turning on the XOSC_HF bias current allowing a DC bias point to be provided to the clipped-sine wave clock signal on external input.
12TCXO_MODER/W0hIf this register is 1 when BYPASS is 1, this will enable clock qualification on the TCXO clock on external input. This register has no effect when BYPASS is 0.
11-10RESERVEDR0hReserved
9-8PEAK_DET_ITRIMR/W0hInternal. Only to be used through TI provided API.
7RESERVEDR0hReserved
6BYPASSR/W0hInternal. Only to be used through TI provided API.
5RESERVEDR0hReserved
4-2HP_BUF_ITRIMR/W0hInternal. Only to be used through TI provided API.
1-0LP_BUF_ITRIMR/W0hInternal. Only to be used through TI provided API.

8.8.1.12 LFOSCCTL Register (Offset = 2Ch) [Reset = 00000000h]

LFOSCCTL is shown in Figure 8-18 and described in Table 8-21.

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Low Frequency Oscillator Control

Figure 8-18 LFOSCCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
XOSCLF_REGULATOR_TRIMXOSCLF_CMIRRWR_RATIORESERVED
R/W-0hR/W-0hR-0h
15141312111098
RESERVEDRCOSCLF_RTUNE_TRIM
R-0hR/W-0h
76543210
RCOSCLF_CTUNE_TRIM
R/W-0h
Table 8-21 LFOSCCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-22XOSCLF_REGULATOR_TRIMR/W0hInternal. Only to be used through TI provided API.
21-18XOSCLF_CMIRRWR_RATIOR/W0hInternal. Only to be used through TI provided API.
17-10RESERVEDR0hReserved
9-8RCOSCLF_RTUNE_TRIMR/W0hInternal. Only to be used through TI provided API.
7-0RCOSCLF_CTUNE_TRIMR/W0hInternal. Only to be used through TI provided API.

8.8.1.13 RCOSCHFCTL Register (Offset = 30h) [Reset = 00000000h]

RCOSCHFCTL is shown in Figure 8-19 and described in Table 8-22.

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RCOSCHF Control

Figure 8-19 RCOSCHFCTL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RCOSCHF_CTRIMRESERVED
R/W-0hR-0h
Table 8-22 RCOSCHFCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8RCOSCHF_CTRIMR/W0hInternal. Only to be used through TI provided API.
7-0RESERVEDR0hReserved

8.8.1.14 RCOSCMFCTL Register (Offset = 34h) [Reset = 00000000h]

RCOSCMFCTL is shown in Figure 8-20 and described in Table 8-23.

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RCOSC_MF Control

Figure 8-20 RCOSCMFCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RCOSC_MF_CAP_ARRAYRCOSC_MF_REG_SEL
R/W-0hR/W-0h
76543210
RCOSC_MF_RES_COARSERCOSC_MF_RES_FINERCOSC_MF_BIAS_ADJ
R/W-0hR/W-0hR/W-0h
Table 8-23 RCOSCMFCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-9RCOSC_MF_CAP_ARRAYR/W0hAdjust RCOSC_MF capacitor array.
0x0: nominal frequency, 0.625pF
0x40: highest frequency, 0.125pF
0x3F: lowest frequency, 1.125pF
8RCOSC_MF_REG_SELR/W0hChoose regulator type.
0: default
1: alternate
7-6RCOSC_MF_RES_COARSER/W0hSelect coarse resistor for frequency adjustment.
0x0: 400kΩs, default
0x1: 300kΩs, min
0x2: 600kΩs, max
0x3: 500kΩs
5-4RCOSC_MF_RES_FINER/W0hSelect fine resistor for frequency adjustment.
0x0: 11kΩs, minimum resistance, max freq
0x1: 13kΩs
0x2: 16kΩs
0x3: 20kΩs, max resistance, min freq
3-0RCOSC_MF_BIAS_ADJR/W0hAdjusts bias current to RCOSC_MF.
0x8 minimum current
0x0 default current
0x7 maximum current

8.8.1.15 STAT0 Register (Offset = 3Ch) [Reset = 00000000h]

STAT0 is shown in Figure 8-21 and described in Table 8-24.

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Status 0
This register contains status signals from OSC_DIG

Figure 8-21 STAT0 Register
3130292827262524
RESERVEDSCLK_LF_SRCSCLK_HF_SRCRESERVED
R-0hR-0hR-0hR-0h
2322212019181716
RESERVEDRCOSC_HF_ENRCOSC_LF_ENXOSC_LF_ENCLK_DCDC_RDYCLK_DCDC_RDY_ACKSCLK_HF_LOSSSCLK_LF_LOSS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
XOSC_HF_ENRESERVEDXB_48M_CLK_ENRESERVEDXOSC_HF_LP_BUF_ENXOSC_HF_HP_BUF_ENRESERVEDADC_THMET
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
ADC_DATA_READYADC_DATAPENDINGSCLKHFSWITCHING
R-0hR-0hR-0h
Table 8-24 STAT0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30-29SCLK_LF_SRCR0hIndicates source for the sclk_lf
0h = Low frequency clock derived from High Frequency RCOSC
1h = Low frequency clock derived from High Frequency XOSC
2h = Low frequency RCOSC
3h = Low frequency XOSC
28SCLK_HF_SRCR0hIndicates source for the sclk_hf
0h = High frequency RCOSC clock
1h = High frequency XOSC
27-23RESERVEDR0hReserved
22RCOSC_HF_ENR0hRCOSC_HF_EN
21RCOSC_LF_ENR0hRCOSC_LF_EN
20XOSC_LF_ENR0hXOSC_LF_EN
19CLK_DCDC_RDYR0hCLK_DCDC_RDY
18CLK_DCDC_RDY_ACKR0hCLK_DCDC_RDY_ACK
17SCLK_HF_LOSSR0hIndicates sclk_hf is lost
16SCLK_LF_LOSSR0hIndicates sclk_lf is lost
15XOSC_HF_ENR0hIndicates that XOSC_HF is enabled.
14RESERVEDR0hReserved
13XB_48M_CLK_ENR0hIndicates that the 48MHz clock from the DOUBLER is enabled.
It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler bypass for the 48MHz crystal).
12RESERVEDR0hReserved
11XOSC_HF_LP_BUF_ENR0hXOSC_HF_LP_BUF_EN
10XOSC_HF_HP_BUF_ENR0hXOSC_HF_HP_BUF_EN
9RESERVEDR0hReserved
8ADC_THMETR0hADC_THMET
7ADC_DATA_READYR0hindicates when adc_data is ready.
6-1ADC_DATAR0hadc_data
0PENDINGSCLKHFSWITCHINGR0hIndicates when SCLK_HF clock source is ready to be switched

8.8.1.16 STAT1 Register (Offset = 40h) [Reset = 00000000h]

STAT1 is shown in Figure 8-22 and described in Table 8-25.

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Status 1
This register contains status signals from OSC_DIG

Figure 8-22 STAT1 Register
3130292827262524
RAMPSTATEHPM_UPDATE_AMP
R-0hR-0h
2322212019181716
HPM_UPDATE_AMPLPM_UPDATE_AMP
R-0hR-0h
15141312111098
FORCE_RCOSC_HFSCLK_HF_ENSCLK_MF_ENACLK_ADC_ENACLK_TDC_ENACLK_REF_ENCLK_CHP_ENCLK_DCDC_EN
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
SCLK_HF_GOODSCLK_MF_GOODSCLK_LF_GOODACLK_ADC_GOODACLK_TDC_GOODACLK_REF_GOODCLK_CHP_GOODCLK_DCDC_GOOD
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-25 STAT1 Register Field Descriptions
BitFieldTypeResetDescription
31-28RAMPSTATER0hAMPCOMP FSM State
0h = RESET
1h = INITIALIZATION
2h = HPM_RAMP1
3h = HPM_RAMP2
4h = HPM_RAMP3
5h = HPM_UPDATE
6h = IDAC_INCREMENT
7h = IBIAS_CAP_UPDATE
8h = IBIAS_DECREMENT_WITH_MEASURE
9h = LPM_UPDATE
Ah = IBIAS_INCREMENT
Bh = IDAC_DECREMENT_WITH_MEASURE
Ch = DUMMY_TO_INIT_1
Dh = FAST_START
Eh = FAST_START_SETTLE
27-22HPM_UPDATE_AMPR0hXOSC_HF amplitude during HPM_UPDATE state.
When amplitude compensation of XOSC_HF is enabled in high performance mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value.
21-16LPM_UPDATE_AMPR0hXOSC_HF amplitude during LPM_UPDATE state
When amplitude compensation of XOSC_HF is enabled in low power mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value.
15FORCE_RCOSC_HFR0hforce_rcosc_hf
14SCLK_HF_ENR0hSCLK_HF_EN
13SCLK_MF_ENR0hSCLK_MF_EN
12ACLK_ADC_ENR0hACLK_ADC_EN
11ACLK_TDC_ENR0hACLK_TDC_EN
10ACLK_REF_ENR0hACLK_REF_EN
9CLK_CHP_ENR0hCLK_CHP_EN
8CLK_DCDC_ENR0hCLK_DCDC_EN
7SCLK_HF_GOODR0hSCLK_HF_GOOD
6SCLK_MF_GOODR0hSCLK_MF_GOOD
5SCLK_LF_GOODR0hSCLK_LF_GOOD
4ACLK_ADC_GOODR0hACLK_ADC_GOOD
3ACLK_TDC_GOODR0hACLK_TDC_GOOD
2ACLK_REF_GOODR0hACLK_REF_GOOD.
1CLK_CHP_GOODR0hCLK_CHP_GOOD
0CLK_DCDC_GOODR0hCLK_DCDC_GOOD

8.8.1.17 STAT2 Register (Offset = 44h) [Reset = 00000000h]

STAT2 is shown in Figure 8-23 and described in Table 8-26.

Return to the Summary Table.

Status 2
This register contains status signals from AMPCOMP FSM

Figure 8-23 STAT2 Register
3130292827262524
ADC_DCBIASHPM_RAMP1_THMETHPM_RAMP2_THMET
R-0hR-0hR-0h
2322212019181716
HPM_RAMP3_THMETRESERVED
R-0hR-0h
15141312111098
RAMPSTATERESERVED
R-0hR-0h
76543210
RESERVEDAMPCOMP_REQXOSC_HF_AMPGOODXOSC_HF_FREQGOODXOSC_HF_RF_FREQGOOD
R-0hR-0hR-0hR-0hR-0h
Table 8-26 STAT2 Register Field Descriptions
BitFieldTypeResetDescription
31-26ADC_DCBIASR0hDC Bias read by RADC during SAR mode
The value is an unsigned integer. It is used for debug only.
25HPM_RAMP1_THMETR0hIndication of threshold is met for hpm_ramp1
24HPM_RAMP2_THMETR0hIndication of threshold is met for hpm_ramp2
23HPM_RAMP3_THMETR0hIndication of threshold is met for hpm_ramp3
22-16RESERVEDR0hReserved
15-12RAMPSTATER0hxosc_hf amplitude compensation FSM
This is identical to STAT1.RAMPSTATE. See that description for encoding.
11-4RESERVEDR0hReserved
3AMPCOMP_REQR0hampcomp_req
2XOSC_HF_AMPGOODR0hamplitude of xosc_hf is within the required threshold (set by DDI). Not used for anything just for debug/status
1XOSC_HF_FREQGOODR0hfrequency of xosc_hf is good to use for the digital clocks
0XOSC_HF_RF_FREQGOODR0hfrequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations. Used for SW to start synthesizer.