SWCU185G January   2018  – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  3. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4F
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Sensor Controller
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  4. 3 Arm® Cortex®-M4F Processor
    1. 3.1 Arm® Cortex®-M4F Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Floating Point Unit (FPU)
      5. 3.3.5 Memory Protection Unit (MPU)
      6. 3.3.6 Arm® Cortex®-M4F System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4F Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4F Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Floating Point Unit (FPU)
      1. 3.7.1 About the FPU
      2. 3.7.2 FPU Functional Description
        1. 3.7.2.1 FPU Views of the Register Bank
        2. 3.7.2.2 Modes of Operation
          1. 3.7.2.2.1 Full-Compliance Mode
          2. 3.7.2.2.2 Flush-to-Zero Mode
          3. 3.7.2.2.3 Default NaN Mode
        3. 3.7.2.3 FPU Instruction Set
        4. 3.7.2.4 Compliance With the IEEE 754 Standard
        5. 3.7.2.5 Complete Implementation of the IEEE 754 Standard
        6. 3.7.2.6 IEEE 754 Standard Implementation Choices
          1. 3.7.2.6.1 NaN Handling
          2. 3.7.2.6.2 Comparisons
          3. 3.7.2.6.3 Underflow
        7. 3.7.2.7 Exceptions
      3. 3.7.3 FPU Programmers Model
        1. 3.7.3.1 Enabling the FPU
          1. 3.7.3.1.1 Enabling the FPU
    8. 3.8 Memory Protection Unit (MPU)
      1. 3.8.1 About the MPU
      2. 3.8.2 MPU Functional Description
      3. 3.8.3 MPU Programmers Model
    9. 3.9 Arm® Cortex®-M4F Processor Registers
      1. 3.9.1 CPU_DWT Registers
      2. 3.9.2 CPU_FPB Registers
      3. 3.9.3 CPU_ITM Registers
      4. 3.9.4 CPU_SCS Registers
      5. 3.9.5 CPU_TPIU Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Arm® Cortex®-M4F Peripherals
    1. 5.1 Arm® Cortex®-M4F Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  7. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  8. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  9. 8 Power, Reset, and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 DDI_0_OSC Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  10. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  11. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM_MMR Registers
      2. 10.7.2 SRAM Registers
  12. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  13. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  14. 13Cryptography
    1. 13.1 AES and Hash Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master PROT Enable
          1. 13.5.4.2.1 Master PROT-Privileged Access-Enable
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
        5. 13.5.6.5 Hash Engine
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Hashing
        1. 13.7.3.1 Data Format and Byte Order
        2. 13.7.3.2 Basic Hash With Data From DMA
          1. 13.7.3.2.1 New Hash Session With Digest Read Through Slave
          2. 13.7.3.2.2 New Hash Session With Digest to External Memory
          3. 13.7.3.2.3 Resumed Hash Session
        3. 13.7.3.3 HMAC
          1. 13.7.3.3.1 Secure HMAC
        4. 13.7.3.4 Alternative Basic Hash Where Data Originates From Slave Interface
          1. 13.7.3.4.1 New Hash Session
          2. 13.7.3.4.2 Resumed Hash Session
      4. 13.7.4 Encryption and Decryption
        1. 13.7.4.1 Data Format and Byte Order
        2. 13.7.4.2 Key Store
          1. 13.7.4.2.1 Load Keys From External Memory
        3. 13.7.4.3 Basic AES Modes
          1. 13.7.4.3.1 AES-ECB
          2. 13.7.4.3.2 AES-CBC
          3. 13.7.4.3.3 AES-CTR
          4. 13.7.4.3.4 Programming Sequence With DMA Data
        4. 13.7.4.4 CBC-MAC
          1. 13.7.4.4.1 Programming Sequence for CBC-MAC
        5. 13.7.4.5 AES-CCM
          1. 13.7.4.5.1 Programming Sequence for AES-CCM
        6. 13.7.4.6 AES-GCM
          1. 13.7.4.6.1 Programming Sequence for AES-GCM
      5. 13.7.5 Exceptions Handling
        1. 13.7.5.1 Soft Reset
        2. 13.7.5.2 External Port Errors
        3. 13.7.5.3 Key Store Errors
          1. 13.7.5.3.1 PKA Engine
          2. 13.7.5.3.2 Functional Description
            1. 13.7.5.3.2.1 Module Architecture
          3. 13.7.5.3.3 PKA RAM
            1. 13.7.5.3.3.1 PKCP Operations
            2. 13.7.5.3.3.2 Sequencer Operations
              1. 13.7.5.3.3.2.1 Modular Exponentiation Operations
              2. 13.7.5.3.3.2.2 Modular Inversion Operation
              3. 13.7.5.3.3.2.3 Performance
              4. 13.7.5.3.3.2.4 ECC Operations
              5. 13.7.5.3.3.2.5 Performance
              6. 13.7.5.3.3.2.6 ExpMod Performance
              7. 13.7.5.3.3.2.7 Modular Inversion Performance
              8. 13.7.5.3.3.2.8 ECC Operation Performance
            3. 13.7.5.3.3.3 Sequencer ROM Behavior and Interfaces
            4. 13.7.5.3.3.4 Register Configurations
            5. 13.7.5.3.3.5 Operation Sequence
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  15. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 UDMA Registers
  17. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  18. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  19. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  20. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 AIODIO
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 SMPH
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPIM
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
              1. 20.4.7.2.5.1.1 Timer Period and Pulse Width Capture
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.2.1 Center-Aligned PWM Generation by Channel 0
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.3.1 Edge-Aligned PWM Generation by Channel 0
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 COMPA
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 COMPB
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference DAC
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 ISRC
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  24. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

20.8.3 AUX_EVCTL Registers

Table 20-74 lists the memory-mapped registers for the AUX_EVCTL registers. All register offset addresses not listed in Table 20-74 should be considered as reserved locations and the register contents should not be modified.

Table 20-74 AUX_EVCTL Registers
OffsetAcronymRegister NameSection
0hEVSTAT0Event Status 0EVSTAT0 Register (Offset = 0h) [Reset = 00000000h]
4hEVSTAT1Event Status 1EVSTAT1 Register (Offset = 4h) [Reset = 00000000h]
8hEVSTAT2Event Status 2EVSTAT2 Register (Offset = 8h) [Reset = 00000000h]
ChEVSTAT3Event Status 3EVSTAT3 Register (Offset = Ch) [Reset = 00000000h]
10hSCEWEVCFG0Sensor Controller Engine Wait Event Configuration 0SCEWEVCFG0 Register (Offset = 10h) [Reset = 00000000h]
14hSCEWEVCFG1Sensor Controller Engine Wait Event Configuration 1SCEWEVCFG1 Register (Offset = 14h) [Reset = 00000000h]
18hDMACTLDirect Memory Access ControlDMACTL Register (Offset = 18h) [Reset = 00000000h]
20hSWEVSETSoftware Event SetSWEVSET Register (Offset = 20h) [Reset = 00000000h]
24hEVTOAONFLAGSEvents To AON FlagsEVTOAONFLAGS Register (Offset = 24h) [Reset = 00000000h]
28hEVTOAONPOLEvents To AON PolarityEVTOAONPOL Register (Offset = 28h) [Reset = 00000000h]
2ChEVTOAONFLAGSCLREvents To AON ClearEVTOAONFLAGSCLR Register (Offset = 2Ch) [Reset = 00000000h]
30hEVTOMCUFLAGSEvents to MCU FlagsEVTOMCUFLAGS Register (Offset = 30h) [Reset = 00000000h]
34hEVTOMCUPOLEvent To MCU PolarityEVTOMCUPOL Register (Offset = 34h) [Reset = 00000000h]
38hEVTOMCUFLAGSCLREvents To MCU Flags ClearEVTOMCUFLAGSCLR Register (Offset = 38h) [Reset = 00000000h]
3ChCOMBEVTOMCUMASKCombined Event To MCU MaskCOMBEVTOMCUMASK Register (Offset = 3Ch) [Reset = 00000000h]
40hEVOBSCFGEvent Observation ConfigurationEVOBSCFG Register (Offset = 40h) [Reset = 00000000h]
44hPROGDLYProgrammable DelayPROGDLY Register (Offset = 44h) [Reset = 00000000h]
48hMANUALManualMANUAL Register (Offset = 48h) [Reset = 00000000h]
4ChEVSTAT0LEvent Status 0 LowEVSTAT0L Register (Offset = 4Ch) [Reset = 00000000h]
50hEVSTAT0HEvent Status 0 HighEVSTAT0H Register (Offset = 50h) [Reset = 00000000h]
54hEVSTAT1LEvent Status 1 LowEVSTAT1L Register (Offset = 54h) [Reset = 00000000h]
58hEVSTAT1HEvent Status 1 HighEVSTAT1H Register (Offset = 58h) [Reset = 00000000h]
5ChEVSTAT2LEvent Status 2 LowEVSTAT2L Register (Offset = 5Ch) [Reset = 00000000h]
60hEVSTAT2HEvent Status 2 HighEVSTAT2H Register (Offset = 60h) [Reset = 00000000h]
64hEVSTAT3LEvent Status 3 LowEVSTAT3L Register (Offset = 64h) [Reset = 00000000h]
68hEVSTAT3HEvent Status 3 HighEVSTAT3H Register (Offset = 68h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Table 20-75 shows the codes that are used for access types in this section.

Table 20-75 AUX_EVCTL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W0CW
0C		Write
0 to clear
Reset or Default Value
-nValue after reset or the default value

20.8.3.1 EVSTAT0 Register (Offset = 0h) [Reset = 00000000h]

EVSTAT0 is shown in Figure 20-66 and described in Table 20-76.

Return to the Summary Table.

Event Status 0
Register holds events 0 thru 15 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC.
- AUX_SYSIF.
- AUX_AIODIOn.
- EVOBSCFG.

Figure 20-66 EVSTAT0 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AUXIO15AUXIO14AUXIO13AUXIO12AUXIO11AUXIO10AUXIO9AUXIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
AUXIO7AUXIO6AUXIO5AUXIO4AUXIO3AUXIO2AUXIO1AUXIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-76 EVSTAT0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15AUXIO15R0hAUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7.
14AUXIO14R0hAUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6.
13AUXIO13R0hAUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5.
12AUXIO12R0hAUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4.
11AUXIO11R0hAUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3.
10AUXIO10R0hAUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2.
9AUXIO9R0hAUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1.
8AUXIO8R0hAUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0.
7AUXIO7R0hAUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7.
6AUXIO6R0hAUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6.
5AUXIO5R0hAUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5.
4AUXIO4R0hAUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4.
3AUXIO3R0hAUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3.
2AUXIO2R0hAUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2.
1AUXIO1R0hAUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1.
0AUXIO0R0hAUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0.

20.8.3.2 EVSTAT1 Register (Offset = 4h) [Reset = 00000000h]

EVSTAT1 is shown in Figure 20-67 and described in Table 20-77.

Return to the Summary Table.

Event Status 1
Register holds events 16 thru 31 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC.
- AUX_SYSIF.
- AUX_AIODIOn.
- EVOBSCFG.

Figure 20-67 EVSTAT1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AUXIO31AUXIO30AUXIO29AUXIO28AUXIO27AUXIO26AUXIO25AUXIO24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
AUXIO23AUXIO22AUXIO21AUXIO20AUXIO19AUXIO18AUXIO17AUXIO16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-77 EVSTAT1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15AUXIO31R0hAUXIO31 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 7.
14AUXIO30R0hAUXIO30 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 6.
13AUXIO29R0hAUXIO29 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 5.
12AUXIO28R0hAUXIO28 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 4.
11AUXIO27R0hAUXIO27 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 3.
10AUXIO26R0hAUXIO26 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 2.
9AUXIO25R0hAUXIO25 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 1.
8AUXIO24R0hAUXIO24 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 0.
7AUXIO23R0hAUXIO23 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 7.
6AUXIO22R0hAUXIO22 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 6.
5AUXIO21R0hAUXIO21 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 5.
4AUXIO20R0hAUXIO20 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 4.
3AUXIO19R0hAUXIO19 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 3.
2AUXIO18R0hAUXIO18 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 2.
1AUXIO17R0hAUXIO17 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 1.
0AUXIO16R0hAUXIO16 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 0.

20.8.3.3 EVSTAT2 Register (Offset = 8h) [Reset = 00000000h]

EVSTAT2 is shown in Figure 20-68 and described in Table 20-78.

Return to the Summary Table.

Event Status 2
Register holds events 32 thru 47 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC.
- AUX_SYSIF.
- AUX_AIODIOn.
- EVOBSCFG.

Figure 20-68 EVSTAT2 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AUX_COMPBAUX_COMPAMCU_OBSMUX1MCU_OBSMUX0MCU_EVACLK_REFVDDR_RECHARGEMCU_ACTIVE
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
PWR_DWNSCLK_LFAON_BATMON_TEMP_UPDAON_BATMON_BAT_UPDAON_RTC_4KHZAON_RTC_CH2_DLYAON_RTC_CH2MANUAL_EV
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-78 EVSTAT2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15AUX_COMPBR0hComparator B output.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the synchronization rate for this event.
14AUX_COMPAR0hComparator A output.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the synchronization rate for this event.
13MCU_OBSMUX1R0hObservation input 1 from IOC.
This event is configured by IOC:OBSAUXOUTPUT.SEL1.
12MCU_OBSMUX0R0hObservation input 0 from IOC.
This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by IOC:OBSAUXOUTPUT.SEL_MISC.
11MCU_EVR0hEvent from EVENT configured by EVENT:AUXSEL0.
10ACLK_REFR0hTDC reference clock.
It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_SYSIF:TDCREFCLKCTL.REQ.
9VDDR_RECHARGER0hEvent is high during VDDR recharge.
8MCU_ACTIVER0hEvent is high while system(MCU, AUX, or JTAG domains) is active or transitions to active (GLDO or DCDC power supply state). Event is not high during VDDR recharge.
7PWR_DWNR0hEvent is high while system(MCU, AUX, or JTAG domains) is in powerdown (uLDO power supply).
6SCLK_LFR0hSCLK_LF clock
5AON_BATMON_TEMP_UPDR0hEvent is high for two SCLK_MF clock periods when there is an update of AON_BATMON:TEMP.
4AON_BATMON_BAT_UPDR0hEvent is high for two SCLK_MF clock periods when there is an update of AON_BATMON:BAT.
3AON_RTC_4KHZR0hAON_RTC:SUBSEC.VALUE bit 19.
AON_RTC:CTL.RTC_4KHZ_EN enables this event.
2AON_RTC_CH2_DLYR0hAON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration.
1AON_RTC_CH2R0hAON_RTC:EVFLAGS.CH2.
0MANUAL_EVR0hProgrammable event. See MANUAL for description.

20.8.3.4 EVSTAT3 Register (Offset = Ch) [Reset = 00000000h]

EVSTAT3 is shown in Figure 20-69 and described in Table 20-79.

Return to the Summary Table.

Event Status 3
Register holds events 48 thru 63 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC .
- AUX_SYSIF.
- AUX_AIODIOn.
- EVOBSCFG.

Figure 20-69 EVSTAT3 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AUX_TIMER2_CLKSWITCH_RDYAUX_DAC_HOLD_ACTIVEAUX_SMPH_AUTOTAKE_DONEAUX_ADC_FIFO_NOT_EMPTYAUX_ADC_FIFO_ALMOST_FULLAUX_ADC_IRQAUX_ADC_DONEAUX_ISRC_RESET_N
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
AUX_TDC_DONEAUX_TIMER0_EVAUX_TIMER1_EVAUX_TIMER2_PULSEAUX_TIMER2_EV3AUX_TIMER2_EV2AUX_TIMER2_EV1AUX_TIMER2_EV0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-79 EVSTAT3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15AUX_TIMER2_CLKSWITCH_RDYR0hAUX_SYSIF:TIMER2CLKSWITCH.RDY
14AUX_DAC_HOLD_ACTIVER0hAUX_ANAIF:DACSTAT.HOLD_ACTIVE
13AUX_SMPH_AUTOTAKE_DONER0hSee AUX_SMPH:AUTOTAKE.SMPH_ID for description.
12AUX_ADC_FIFO_NOT_EMPTYR0hAUX_ANAIF:ADCFIFOSTAT.EMPTY negated
11AUX_ADC_FIFO_ALMOST_FULLR0hAUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL
10AUX_ADC_IRQR0hThe logical function for this event is configurable.
When DMACTL.EN = 1 :
Event = UDMA0 Channel 7 done event OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW
When DMACTL.EN = 0 :
Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW
Bit 7 in UDMA0:DONEMASK must be 0.
9AUX_ADC_DONER0hAUX_ANAIF ADC conversion done event.
Event is synchronized at AUX bus rate.
8AUX_ISRC_RESET_NR0hAUX_ANAIF:ISRCCTL.RESET_N
7AUX_TDC_DONER0hAUX_TDC:STAT.DONE
6AUX_TIMER0_EVR0hAUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description.
5AUX_TIMER1_EVR0hAUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description.
4AUX_TIMER2_PULSER0hAUX_TIMER2 pulse event.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.
3AUX_TIMER2_EV3R0hAUX_TIMER2 event output 3.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.
2AUX_TIMER2_EV2R0hAUX_TIMER2 event output 2.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.
1AUX_TIMER2_EV1R0hAUX_TIMER2 event output 1.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.
0AUX_TIMER2_EV0R0hAUX_TIMER2 event output 0.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.

20.8.3.5 SCEWEVCFG0 Register (Offset = 10h) [Reset = 00000000h]

SCEWEVCFG0 is shown in Figure 20-70 and described in Table 20-80.

Return to the Summary Table.

Sensor Controller Engine Wait Event Configuration 0
Configuration of this register and SCEWEVCFG1 controls bit index 7 in AUX_SCE:WUSTAT.EV_SIGNALS. This bit can be used by AUX_SCE WEV0, WEV1, BEV0 and BEV1 instructions.
When COMB_EV_EN = 0:
AUX_SCE:WUSTAT.EV_SIGNALS (7) = EV0_SEL event
When COMB_EV_EN = 1:
AUX_SCE:WUSTAT.EV_SIGNALS (7) = ( EV0_SEL event ) OR ( SCEWEVCFG1.EV1_SEL event )
Bit fields SCEWEVCFG1.EV0_POL and SCEWEVCFG1.EV1_POL control the polarity of selected events.
Event combination is useful when there is a need to wait for a certain condition with timeout.

Figure 20-70 SCEWEVCFG0 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCOMB_EV_ENEV0_SEL
R-0hR/W-0hR/W-0h
Table 20-80 SCEWEVCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6COMB_EV_ENR/W0hEvent combination control:
0: Disable event combination.
1: Enable event combination.
5-0EV0_SELR/W0hSelect the event source from the synchronous event bus to be used in event equation.
0h = EVSTAT0.AUXIO0
1h = EVSTAT0.AUXIO1
2h = EVSTAT0.AUXIO2
3h = EVSTAT0.AUXIO3
4h = EVSTAT0.AUXIO4
5h = EVSTAT0.AUXIO5
6h = EVSTAT0.AUXIO6
7h = EVSTAT0.AUXIO7
8h = EVSTAT0.AUXIO8
9h = EVSTAT0.AUXIO9
Ah = EVSTAT0.AUXIO10
Bh = EVSTAT0.AUXIO11
Ch = EVSTAT0.AUXIO12
Dh = EVSTAT0.AUXIO13
Eh = EVSTAT0.AUXIO14
Fh = EVSTAT0.AUXIO15
10h = EVSTAT1.AUXIO16
11h = EVSTAT1.AUXIO17
12h = EVSTAT1.AUXIO18
13h = EVSTAT1.AUXIO19
14h = EVSTAT1.AUXIO20
15h = EVSTAT1.AUXIO21
16h = EVSTAT1.AUXIO22
17h = EVSTAT1.AUXIO23
18h = EVSTAT1.AUXIO24
19h = EVSTAT1.AUXIO25
1Ah = EVSTAT1.AUXIO26
1Bh = EVSTAT1.AUXIO27
1Ch = EVSTAT1.AUXIO28
1Dh = EVSTAT1.AUXIO29
1Eh = EVSTAT1.AUXIO30
1Fh = EVSTAT1.AUXIO31
20h = Programmable delay event as described in PROGDLY
21h = EVSTAT2.AON_RTC_CH2
22h = EVSTAT2.AON_RTC_CH2_DLY
23h = EVSTAT2.AON_RTC_4KHZ
24h = EVSTAT2.AON_BATMON_BAT_UPD
25h = EVSTAT2.AON_BATMON_TEMP_UPD
26h = EVSTAT2.SCLK_LF
27h = EVSTAT2.PWR_DWN
28h = EVSTAT2.MCU_ACTIVE
29h = EVSTAT2.VDDR_RECHARGE
2Ah = EVSTAT2.ACLK_REF
2Bh = EVSTAT2.MCU_EV
2Ch = EVSTAT2.MCU_OBSMUX0
2Dh = EVSTAT2.MCU_OBSMUX1
2Eh = EVSTAT2.AUX_COMPA
2Fh = EVSTAT2.AUX_COMPB
30h = EVSTAT3.AUX_TIMER2_EV0
31h = EVSTAT3.AUX_TIMER2_EV1
32h = EVSTAT3.AUX_TIMER2_EV2
33h = EVSTAT3.AUX_TIMER2_EV3
34h = EVSTAT3.AUX_TIMER2_PULSE
35h = EVSTAT3.AUX_TIMER1_EV
36h = EVSTAT3.AUX_TIMER0_EV
37h = EVSTAT3.AUX_TDC_DONE
38h = EVSTAT3.AUX_ISRC_RESET_N
39h = EVSTAT3.AUX_ADC_DONE
3Ah = EVSTAT3.AUX_ADC_IRQ
3Bh = EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
3Ch = EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
3Dh = EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
3Eh = EVSTAT3.AUX_DAC_HOLD_ACTIVE
3Fh = EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY

20.8.3.6 SCEWEVCFG1 Register (Offset = 14h) [Reset = 00000000h]

SCEWEVCFG1 is shown in Figure 20-71 and described in Table 20-81.

Return to the Summary Table.

Sensor Controller Engine Wait Event Configuration 1
See SCEWEVCFG0 for description.

Figure 20-71 SCEWEVCFG1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
EV0_POLEV1_POLEV1_SEL
R/W-0hR/W-0hR/W-0h
Table 20-81 SCEWEVCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7EV0_POLR/W0hPolarity of SCEWEVCFG0.EV0_SEL event.
When SCEWEVCFG0.COMB_EV_EN is 0:
0: Non-inverted.
1: Non-inverted.
When SCEWEVCFG0.COMB_EV_EN is 1.
0: Non-inverted.
1: Inverted.
6EV1_POLR/W0hPolarity of EV1_SEL event.
When SCEWEVCFG0.COMB_EV_EN is 0:
0: Non-inverted.
1: Non-inverted.
When SCEWEVCFG0.COMB_EV_EN is 1.
0: Non-inverted.
1: Inverted.
5-0EV1_SELR/W0hSelect the event source from the synchronous event bus to be used in event equation.
0h = EVSTAT0.AUXIO0
1h = EVSTAT0.AUXIO1
2h = EVSTAT0.AUXIO2
3h = EVSTAT0.AUXIO3
4h = EVSTAT0.AUXIO4
5h = EVSTAT0.AUXIO5
6h = EVSTAT0.AUXIO6
7h = EVSTAT0.AUXIO7
8h = EVSTAT0.AUXIO8
9h = EVSTAT0.AUXIO9
Ah = EVSTAT0.AUXIO10
Bh = EVSTAT0.AUXIO11
Ch = EVSTAT0.AUXIO12
Dh = EVSTAT0.AUXIO13
Eh = EVSTAT0.AUXIO14
Fh = EVSTAT0.AUXIO15
10h = EVSTAT1.AUXIO16
11h = EVSTAT1.AUXIO17
12h = EVSTAT1.AUXIO18
13h = EVSTAT1.AUXIO19
14h = EVSTAT1.AUXIO20
15h = EVSTAT1.AUXIO21
16h = EVSTAT1.AUXIO22
17h = EVSTAT1.AUXIO23
18h = EVSTAT1.AUXIO24
19h = EVSTAT1.AUXIO25
1Ah = EVSTAT1.AUXIO26
1Bh = EVSTAT1.AUXIO27
1Ch = EVSTAT1.AUXIO28
1Dh = EVSTAT1.AUXIO29
1Eh = EVSTAT1.AUXIO30
1Fh = EVSTAT1.AUXIO31
20h = Programmable delay event as described in PROGDLY
21h = EVSTAT2.AON_RTC_CH2
22h = EVSTAT2.AON_RTC_CH2_DLY
23h = EVSTAT2.AON_RTC_4KHZ
24h = EVSTAT2.AON_BATMON_BAT_UPD
25h = EVSTAT2.AON_BATMON_TEMP_UPD
26h = EVSTAT2.SCLK_LF
27h = EVSTAT2.PWR_DWN
28h = EVSTAT2.MCU_ACTIVE
29h = EVSTAT2.VDDR_RECHARGE
2Ah = EVSTAT2.ACLK_REF
2Bh = EVSTAT2.MCU_EV
2Ch = EVSTAT2.MCU_OBSMUX0
2Dh = EVSTAT2.MCU_OBSMUX1
2Eh = EVSTAT2.AUX_COMPA
2Fh = EVSTAT2.AUX_COMPB
30h = EVSTAT3.AUX_TIMER2_EV0
31h = EVSTAT3.AUX_TIMER2_EV1
32h = EVSTAT3.AUX_TIMER2_EV2
33h = EVSTAT3.AUX_TIMER2_EV3
34h = EVSTAT3.AUX_TIMER2_PULSE
35h = EVSTAT3.AUX_TIMER1_EV
36h = EVSTAT3.AUX_TIMER0_EV
37h = EVSTAT3.AUX_TDC_DONE
38h = EVSTAT3.AUX_ISRC_RESET_N
39h = EVSTAT3.AUX_ADC_DONE
3Ah = EVSTAT3.AUX_ADC_IRQ
3Bh = EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
3Ch = EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
3Dh = EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
3Eh = EVSTAT3.AUX_DAC_HOLD_ACTIVE
3Fh = EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY

20.8.3.7 DMACTL Register (Offset = 18h) [Reset = 00000000h]

DMACTL is shown in Figure 20-72 and described in Table 20-82.

Return to the Summary Table.

Direct Memory Access Control

Figure 20-72 DMACTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDREQ_MODEENSEL
R-0hR/W-0hR/W-0hR/W-0h
Table 20-82 DMACTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2REQ_MODER/W0hUDMA0 Request mode
0h = Burst requests are generated on UDMA0 channel 7 when the condition configured in SEL is met.
1h = Single requests are generated on UDMA0 channel 7 when the condition configured in SEL is met.
1ENR/W0huDMA ADC interface enable.
0: Disable UDMA0 interface to ADC.
1: Enable UDMA0 interface to ADC.
0SELR/W0hSelect FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data.
0h = UDMA0 trigger event will be generated when there are samples in the ADC FIFO.
1h = UDMA0 trigger event will be generated when the ADC FIFO is almost full (3/4 full).

20.8.3.8 SWEVSET Register (Offset = 20h) [Reset = 00000000h]

SWEVSET is shown in Figure 20-73 and described in Table 20-83.

Return to the Summary Table.

Software Event Set
Set software event flags from AUX domain to AON and MCU domains. CPUs in MCU domain can read the event flags from EVTOAONFLAGS and clear them in EVTOAONFLAGSCLR.
Use of these event flags is software-defined.

Figure 20-73 SWEVSET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSWEV2SWEV1SWEV0
R-0hW-0hW-0hW-0h
Table 20-83 SWEVSET Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2SWEV2W0hSoftware event flag 2.
0: No effect.
1: Set software event flag 2.
1SWEV1W0hSoftware event flag 1.
0: No effect.
1: Set software event flag 1.
0SWEV0W0hSoftware event flag 0.
0: No effect.
1: Set software event flag 0.

20.8.3.9 EVTOAONFLAGS Register (Offset = 24h) [Reset = 00000000h]

EVTOAONFLAGS is shown in Figure 20-74 and described in Table 20-84.

Return to the Summary Table.

Events To AON Flags
This register contains a collection of event flags routed to AON_EVENT.
To clear an event flag, write to EVTOAONFLAGSCLR or write 0 to event flag in this register.

Figure 20-74 EVTOAONFLAGS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAUX_TIMER1_EV
R-0hR/W0C-0h
76543210
AUX_TIMER0_EVAUX_TDC_DONEAUX_ADC_DONEAUX_COMPBAUX_COMPASWEV2SWEV1SWEV0
R/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0h
Table 20-84 EVTOAONFLAGS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8AUX_TIMER1_EVR/W0C0hThis event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV.
7AUX_TIMER0_EVR/W0C0hThis event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV.
6AUX_TDC_DONER/W0C0hThis event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE.
5AUX_ADC_DONER/W0C0hThis event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE.
4AUX_COMPBR/W0C0hThis event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB.
3AUX_COMPAR/W0C0hThis event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA.
2SWEV2R/W0C0hThis event flag is set when software writes a 1 to SWEVSET.SWEV2.
1SWEV1R/W0C0hThis event flag is set when software writes a 1 to SWEVSET.SWEV1.
0SWEV0R/W0C0hThis event flag is set when software writes a 1 to SWEVSET.SWEV0.

20.8.3.10 EVTOAONPOL Register (Offset = 28h) [Reset = 00000000h]

EVTOAONPOL is shown in Figure 20-75 and described in Table 20-85.

Return to the Summary Table.

Events To AON Polarity
Event source polarity configuration for EVTOAONFLAGS.

Figure 20-75 EVTOAONPOL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAUX_TIMER1_EV
R-0hR/W-0h
76543210
AUX_TIMER0_EVAUX_TDC_DONEAUX_ADC_DONEAUX_COMPBAUX_COMPARESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 20-85 EVTOAONPOL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8AUX_TIMER1_EVR/W0hSelect the level of EVSTAT3.AUX_TIMER1_EV that sets EVTOAONFLAGS.AUX_TIMER1_EV.
0h = High level
1h = Low level
7AUX_TIMER0_EVR/W0hSelect the level of EVSTAT3.AUX_TIMER0_EV that sets EVTOAONFLAGS.AUX_TIMER0_EV.
0h = High level
1h = Low level
6AUX_TDC_DONER/W0hSelect level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE.
0h = High level
1h = Low level
5AUX_ADC_DONER/W0hSelect the level of EVSTAT3.AUX_ADC_DONE that sets EVTOAONFLAGS.AUX_ADC_DONE.
0h = High level
1h = Low level
4AUX_COMPBR/W0hSelect the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB.
0h = Rising edge
1h = Falling edge
3AUX_COMPAR/W0hSelect the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA.
0h = Rising edge
1h = Falling edge
2-0RESERVEDR0hReserved

20.8.3.11 EVTOAONFLAGSCLR Register (Offset = 2Ch) [Reset = 00000000h]

EVTOAONFLAGSCLR is shown in Figure 20-76 and described in Table 20-86.

Return to the Summary Table.

Events To AON Clear
Clear event flags in EVTOAONFLAGS.
In order to clear a level sensitive event flag, the event must be deasserted.

Figure 20-76 EVTOAONFLAGSCLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAUX_TIMER1_EV
R-0hW-0h
76543210
AUX_TIMER0_EVAUX_TDC_DONEAUX_ADC_DONEAUX_COMPBAUX_COMPASWEV2SWEV1SWEV0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 20-86 EVTOAONFLAGSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8AUX_TIMER1_EVW0hWrite 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV.
Read value is 0.
7AUX_TIMER0_EVW0hWrite 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV.
Read value is 0.
6AUX_TDC_DONEW0hWrite 1 to clear EVTOAONFLAGS.AUX_TDC_DONE.
Read value is 0.
5AUX_ADC_DONEW0hWrite 1 to clear EVTOAONFLAGS.AUX_ADC_DONE.
Read value is 0.
4AUX_COMPBW0hWrite 1 to clear EVTOAONFLAGS.AUX_COMPB.
Read value is 0.
3AUX_COMPAW0hWrite 1 to clear EVTOAONFLAGS.AUX_COMPA.
Read value is 0.
2SWEV2W0hWrite 1 to clear EVTOAONFLAGS.SWEV2.
Read value is 0.
1SWEV1W0hWrite 1 to clear EVTOAONFLAGS.SWEV1.
Read value is 0.
0SWEV0W0hWrite 1 to clear EVTOAONFLAGS.SWEV0.
Read value is 0.

20.8.3.12 EVTOMCUFLAGS Register (Offset = 30h) [Reset = 00000000h]

EVTOMCUFLAGS is shown in Figure 20-77 and described in Table 20-87.

Return to the Summary Table.

Events to MCU Flags
This register contains a collection of event flags routed to MCU domain.
To clear an event flag, write to EVTOMCUFLAGSCLR or write 0 to event flag in this register. Follow procedure described in AUX_SYSIF:WUCLR to clear AUX_WU_EV event flag.

Figure 20-77 EVTOMCUFLAGS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AUX_TIMER2_PULSEAUX_TIMER2_EV3AUX_TIMER2_EV2AUX_TIMER2_EV1AUX_TIMER2_EV0AUX_ADC_IRQMCU_OBSMUX0AUX_ADC_FIFO_ALMOST_FULL
R/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0h
76543210
AUX_ADC_DONEAUX_SMPH_AUTOTAKE_DONEAUX_TIMER1_EVAUX_TIMER0_EVAUX_TDC_DONEAUX_COMPBAUX_COMPAAUX_WU_EV
R/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0h
Table 20-87 EVTOMCUFLAGS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15AUX_TIMER2_PULSER/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE occurs on EVSTAT3.AUX_TIMER2_PULSE.
14AUX_TIMER2_EV3R/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 occurs on EVSTAT3.AUX_TIMER2_EV3.
13AUX_TIMER2_EV2R/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 occurs on EVSTAT3.AUX_TIMER2_EV2.
12AUX_TIMER2_EV1R/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 occurs on EVSTAT3.AUX_TIMER2_EV1.
11AUX_TIMER2_EV0R/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 occurs on EVSTAT3.AUX_TIMER2_EV0.
10AUX_ADC_IRQR/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs on EVSTAT3.AUX_ADC_IRQ.
9MCU_OBSMUX0R/W0C0hThis event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT2.MCU_OBSMUX0.
8AUX_ADC_FIFO_ALMOST_FULLR/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL.
7AUX_ADC_DONER/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE.
6AUX_SMPH_AUTOTAKE_DONER/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE.
5AUX_TIMER1_EVR/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV.
4AUX_TIMER0_EVR/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV.
3AUX_TDC_DONER/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE.
2AUX_COMPBR/W0C0hThis event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB.
1AUX_COMPAR/W0C0hThis event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA.
0AUX_WU_EVR/W0C0hThis event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on reduction-OR of the AUX_SYSIF:WUFLAGS register.

20.8.3.13 EVTOMCUPOL Register (Offset = 34h) [Reset = 00000000h]

EVTOMCUPOL is shown in Figure 20-78 and described in Table 20-88.

Return to the Summary Table.

Event To MCU Polarity
Event source polarity configuration for EVTOMCUFLAGS.

Figure 20-78 EVTOMCUPOL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AUX_TIMER2_PULSEAUX_TIMER2_EV3AUX_TIMER2_EV2AUX_TIMER2_EV1AUX_TIMER2_EV0AUX_ADC_IRQMCU_OBSMUX0AUX_ADC_FIFO_ALMOST_FULL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
AUX_ADC_DONEAUX_SMPH_AUTOTAKE_DONEAUX_TIMER1_EVAUX_TIMER0_EVAUX_TDC_DONEAUX_COMPBAUX_COMPAAUX_WU_EV
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-88 EVTOMCUPOL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15AUX_TIMER2_PULSER/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE.
0h = High level
1h = Low level
14AUX_TIMER2_EV3R/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3.
0h = High level
1h = Low level
13AUX_TIMER2_EV2R/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2.
0h = High level
1h = Low level
12AUX_TIMER2_EV1R/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1.
0h = High level
1h = Low level
11AUX_TIMER2_EV0R/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0.
0h = High level
1h = Low level
10AUX_ADC_IRQR/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ.
0h = High level
1h = Low level
9MCU_OBSMUX0R/W0hSelect the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0.
0h = High level
1h = Low level
8AUX_ADC_FIFO_ALMOST_FULLR/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.
0h = High level
1h = Low level
7AUX_ADC_DONER/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE.
0h = High level
1h = Low level
6AUX_SMPH_AUTOTAKE_DONER/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.
0h = High level
1h = Low level
5AUX_TIMER1_EVR/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV.
0h = High level
1h = Low level
4AUX_TIMER0_EVR/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV.
0h = High level
1h = Low level
3AUX_TDC_DONER/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE.
0h = High level
1h = Low level
2AUX_COMPBR/W0hSelect the event source edge that sets EVTOMCUFLAGS.AUX_COMPB.
0h = Rising edge
1h = Falling edge
1AUX_COMPAR/W0hSelect the event source edge that sets EVTOMCUFLAGS.AUX_COMPA.
0h = Rising edge
1h = Falling edge
0AUX_WU_EVR/W0hSelect the event source level that sets EVTOMCUFLAGS.AUX_WU_EV.
0h = High level
1h = Low level

20.8.3.14 EVTOMCUFLAGSCLR Register (Offset = 38h) [Reset = 00000000h]

EVTOMCUFLAGSCLR is shown in Figure 20-79 and described in Table 20-89.

Return to the Summary Table.

Events To MCU Flags Clear
Clear event flags in EVTOMCUFLAGS.
In order to clear a level sensitive event flag, the event must be deasserted.

Figure 20-79 EVTOMCUFLAGSCLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AUX_TIMER2_PULSEAUX_TIMER2_EV3AUX_TIMER2_EV2AUX_TIMER2_EV1AUX_TIMER2_EV0AUX_ADC_IRQMCU_OBSMUX0AUX_ADC_FIFO_ALMOST_FULL
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
AUX_ADC_DONEAUX_SMPH_AUTOTAKE_DONEAUX_TIMER1_EVAUX_TIMER0_EVAUX_TDC_DONEAUX_COMPBAUX_COMPAAUX_WU_EV
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 20-89 EVTOMCUFLAGSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15AUX_TIMER2_PULSEW0hWrite 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE.
Read value is 0.
14AUX_TIMER2_EV3W0hWrite 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3.
Read value is 0.
13AUX_TIMER2_EV2W0hWrite 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2.
Read value is 0.
12AUX_TIMER2_EV1W0hWrite 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1.
Read value is 0.
11AUX_TIMER2_EV0W0hWrite 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0.
Read value is 0.
10AUX_ADC_IRQW0hWrite 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ.
Read value is 0.
9MCU_OBSMUX0W0hWrite 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0.
Read value is 0.
8AUX_ADC_FIFO_ALMOST_FULLW0hWrite 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.
Read value is 0.
7AUX_ADC_DONEW0hWrite 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE.
Read value is 0.
6AUX_SMPH_AUTOTAKE_DONEW0hWrite 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.
Read value is 0.
5AUX_TIMER1_EVW0hWrite 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV.
Read value is 0.
4AUX_TIMER0_EVW0hWrite 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV.
Read value is 0.
3AUX_TDC_DONEW0hWrite 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE.
Read value is 0.
2AUX_COMPBW0hWrite 1 to clear EVTOMCUFLAGS.AUX_COMPB.
Read value is 0.
1AUX_COMPAW0hWrite 1 to clear EVTOMCUFLAGS.AUX_COMPA.
Read value is 0.
0AUX_WU_EVW0hWrite 1 to clear EVTOMCUFLAGS.AUX_WU_EV.
Read value is 0.

20.8.3.15 COMBEVTOMCUMASK Register (Offset = 3Ch) [Reset = 00000000h]

COMBEVTOMCUMASK is shown in Figure 20-80 and described in Table 20-90.

Return to the Summary Table.

Combined Event To MCU Mask
Select event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU.
The AUX_COMB event is high as long as one or more of the included event flags are set.

Figure 20-80 COMBEVTOMCUMASK Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AUX_TIMER2_PULSEAUX_TIMER2_EV3AUX_TIMER2_EV2AUX_TIMER2_EV1AUX_TIMER2_EV0AUX_ADC_IRQMCU_OBSMUX0AUX_ADC_FIFO_ALMOST_FULL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
AUX_ADC_DONEAUX_SMPH_AUTOTAKE_DONEAUX_TIMER1_EVAUX_TIMER0_EVAUX_TDC_DONEAUX_COMPBAUX_COMPAAUX_WU_EV
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-90 COMBEVTOMCUMASK Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15AUX_TIMER2_PULSER/W0hEVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event.
0: Exclude.
1: Include.
14AUX_TIMER2_EV3R/W0hEVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event.
0: Exclude.
1: Include.
13AUX_TIMER2_EV2R/W0hEVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event.
0: Exclude.
1: Include.
12AUX_TIMER2_EV1R/W0hEVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event.
0: Exclude.
1: Include.
11AUX_TIMER2_EV0R/W0hEVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event.
0: Exclude.
1: Include.
10AUX_ADC_IRQR/W0hEVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event.
0: Exclude.
1: Include.
9MCU_OBSMUX0R/W0hEVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event.
0: Exclude.
1: Include.
8AUX_ADC_FIFO_ALMOST_FULLR/W0hEVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event.
0: Exclude.
1: Include.
7AUX_ADC_DONER/W0hEVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event.
0: Exclude.
1: Include.
6AUX_SMPH_AUTOTAKE_DONER/W0hEVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event.
0: Exclude.
1: Include.
5AUX_TIMER1_EVR/W0hEVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event.
0: Exclude.
1: Include.
4AUX_TIMER0_EVR/W0hEVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event.
0: Exclude.
1: Include.
3AUX_TDC_DONER/W0hEVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event.
0: Exclude.
1: Include.
2AUX_COMPBR/W0hEVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event.
0: Exclude
1: Include.
1AUX_COMPAR/W0hEVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event.
0: Exclude.
1: Include.
0AUX_WU_EVR/W0hEVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event.
0: Exclude.
1: Include.

20.8.3.16 EVOBSCFG Register (Offset = 40h) [Reset = 00000000h]

EVOBSCFG is shown in Figure 20-81 and described in Table 20-91.

Return to the Summary Table.

Event Observation Configuration

Figure 20-81 EVOBSCFG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDEVOBS_SEL
R-0hR/W-0h
Table 20-91 EVOBSCFG Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0EVOBS_SELR/W0hSelect which event from the asynchronous event bus that represents AUX_EV_OBS in AUX_AIODIOn.
0h = EVSTAT0.AUXIO0
1h = EVSTAT0.AUXIO1
2h = EVSTAT0.AUXIO2
3h = EVSTAT0.AUXIO3
4h = EVSTAT0.AUXIO4
5h = EVSTAT0.AUXIO5
6h = EVSTAT0.AUXIO6
7h = EVSTAT0.AUXIO7
8h = EVSTAT0.AUXIO8
9h = EVSTAT0.AUXIO9
Ah = EVSTAT0.AUXIO10
Bh = EVSTAT0.AUXIO11
Ch = EVSTAT0.AUXIO12
Dh = EVSTAT0.AUXIO13
Eh = EVSTAT0.AUXIO14
Fh = EVSTAT0.AUXIO15
10h = EVSTAT1.AUXIO16
11h = EVSTAT1.AUXIO17
12h = EVSTAT1.AUXIO18
13h = EVSTAT1.AUXIO19
14h = EVSTAT1.AUXIO20
15h = EVSTAT1.AUXIO21
16h = EVSTAT1.AUXIO22
17h = EVSTAT1.AUXIO23
18h = EVSTAT1.AUXIO24
19h = EVSTAT1.AUXIO25
1Ah = EVSTAT1.AUXIO26
1Bh = EVSTAT1.AUXIO27
1Ch = EVSTAT1.AUXIO28
1Dh = EVSTAT1.AUXIO29
1Eh = EVSTAT1.AUXIO30
1Fh = EVSTAT1.AUXIO31
20h = EVSTAT2.MANUAL_EV
21h = EVSTAT2.AON_RTC_CH2
22h = EVSTAT2.AON_RTC_CH2_DLY
23h = EVSTAT2.AON_RTC_4KHZ
24h = EVSTAT2.AON_BATMON_BAT_UPD
25h = EVSTAT2.AON_BATMON_TEMP_UPD
26h = EVSTAT2.SCLK_LF
27h = EVSTAT2.PWR_DWN
28h = EVSTAT2.MCU_ACTIVE
29h = EVSTAT2.VDDR_RECHARGE
2Ah = EVSTAT2.ACLK_REF
2Bh = EVSTAT2.MCU_EV
2Ch = EVSTAT2.MCU_OBSMUX0
2Dh = EVSTAT2.MCU_OBSMUX1
2Eh = EVSTAT2.AUX_COMPA
2Fh = EVSTAT2.AUX_COMPB
30h = EVSTAT3.AUX_TIMER2_EV0
31h = EVSTAT3.AUX_TIMER2_EV1
32h = EVSTAT3.AUX_TIMER2_EV2
33h = EVSTAT3.AUX_TIMER2_EV3
34h = EVSTAT3.AUX_TIMER2_PULSE
35h = EVSTAT3.AUX_TIMER1_EV
36h = EVSTAT3.AUX_TIMER0_EV
37h = EVSTAT3.AUX_TDC_DONE
38h = EVSTAT3.AUX_ISRC_RESET_N
39h = EVSTAT3.AUX_ADC_DONE
3Ah = EVSTAT3.AUX_ADC_IRQ
3Bh = EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
3Ch = EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
3Dh = EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
3Eh = EVSTAT3.AUX_DAC_HOLD_ACTIVE
3Fh = EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY

20.8.3.17 PROGDLY Register (Offset = 44h) [Reset = 00000000h]

PROGDLY is shown in Figure 20-82 and described in Table 20-92.

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Programmable Delay

Figure 20-82 PROGDLY Register
313029282726252423222120191817161514131211109876543210
RESERVEDVALUE
R-0hR/W-0h
Table 20-92 PROGDLY Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER/W0hVALUE decrements to 0 at a rate of 1 MHz.
The event AUX_PROG_DLY_IDLE is high when VALUE is 0, otherwise it is low.
Only use the programmable delay counter and the AUX_PROG_DLY_IDLE event when AUX_SYSIF:OPMODEACK.ACK equals A or LP.
Decrementation of VALUE halts when either is true:
- AUX_SCE:CTL.DBG_FREEZE_EN is set and system CPU is halted in debug mode.
- AUX_SYSIF:TIMERHALT.PROGDLY is set.

20.8.3.18 MANUAL Register (Offset = 48h) [Reset = 00000000h]

MANUAL is shown in Figure 20-83 and described in Table 20-93.

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Manual
Programmable event.

Figure 20-83 MANUAL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDEV
R-0hR/W-0h
Table 20-93 MANUAL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0EVR/W0hThis bit field sets the value of EVSTAT2.MANUAL_EV.

20.8.3.19 EVSTAT0L Register (Offset = 4Ch) [Reset = 00000000h]

EVSTAT0L is shown in Figure 20-84 and described in Table 20-94.

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Event Status 0 Low

Figure 20-84 EVSTAT0L Register
313029282726252423222120191817161514131211109876543210
RESERVEDALIAS_EV
R-0hR-0h
Table 20-94 EVSTAT0L Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ALIAS_EVR0hAlias of EVSTAT0 event 7 down to 0.

20.8.3.20 EVSTAT0H Register (Offset = 50h) [Reset = 00000000h]

EVSTAT0H is shown in Figure 20-85 and described in Table 20-95.

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Event Status 0 High

Figure 20-85 EVSTAT0H Register
313029282726252423222120191817161514131211109876543210
RESERVEDALIAS_EV
R-0hR-0h
Table 20-95 EVSTAT0H Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ALIAS_EVR0hAlias of EVSTAT0 event 15 down to 8.

20.8.3.21 EVSTAT1L Register (Offset = 54h) [Reset = 00000000h]

EVSTAT1L is shown in Figure 20-86 and described in Table 20-96.

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Event Status 1 Low

Figure 20-86 EVSTAT1L Register
313029282726252423222120191817161514131211109876543210
RESERVEDALIAS_EV
R-0hR-0h
Table 20-96 EVSTAT1L Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ALIAS_EVR0hAlias of EVSTAT1 event 7 down to 0.

20.8.3.22 EVSTAT1H Register (Offset = 58h) [Reset = 00000000h]

EVSTAT1H is shown in Figure 20-87 and described in Table 20-97.

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Event Status 1 High

Figure 20-87 EVSTAT1H Register
313029282726252423222120191817161514131211109876543210
RESERVEDALIAS_EV
R-0hR-0h
Table 20-97 EVSTAT1H Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ALIAS_EVR0hAlias of EVSTAT1 event 15 down to 8.

20.8.3.23 EVSTAT2L Register (Offset = 5Ch) [Reset = 00000000h]

EVSTAT2L is shown in Figure 20-88 and described in Table 20-98.

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Event Status 2 Low

Figure 20-88 EVSTAT2L Register
313029282726252423222120191817161514131211109876543210
RESERVEDALIAS_EV
R-0hR-0h
Table 20-98 EVSTAT2L Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ALIAS_EVR0hAlias of EVSTAT2 event 7 down to 0.

20.8.3.24 EVSTAT2H Register (Offset = 60h) [Reset = 00000000h]

EVSTAT2H is shown in Figure 20-89 and described in Table 20-99.

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Event Status 2 High

Figure 20-89 EVSTAT2H Register
313029282726252423222120191817161514131211109876543210
RESERVEDALIAS_EV
R-0hR-0h
Table 20-99 EVSTAT2H Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ALIAS_EVR0hAlias of EVSTAT2 event 15 down to 8.

20.8.3.25 EVSTAT3L Register (Offset = 64h) [Reset = 00000000h]

EVSTAT3L is shown in Figure 20-90 and described in Table 20-100.

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Event Status 3 Low

Figure 20-90 EVSTAT3L Register
313029282726252423222120191817161514131211109876543210
RESERVEDALIAS_EV
R-0hR-0h
Table 20-100 EVSTAT3L Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ALIAS_EVR0hAlias of EVSTAT3 event 7 down to 0.

20.8.3.26 EVSTAT3H Register (Offset = 68h) [Reset = 00000000h]

EVSTAT3H is shown in Figure 20-91 and described in Table 20-101.

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Event Status 3 High

Figure 20-91 EVSTAT3H Register
313029282726252423222120191817161514131211109876543210
RESERVEDALIAS_EV
R-0hR-0h
Table 20-101 EVSTAT3H Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ALIAS_EVR0hAlias of EVSTAT3 event 15 down to 8.