SWCU185G January   2018  – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  3. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4F
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Sensor Controller
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  4. 3 Arm® Cortex®-M4F Processor
    1. 3.1 Arm® Cortex®-M4F Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Floating Point Unit (FPU)
      5. 3.3.5 Memory Protection Unit (MPU)
      6. 3.3.6 Arm® Cortex®-M4F System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4F Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4F Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Floating Point Unit (FPU)
      1. 3.7.1 About the FPU
      2. 3.7.2 FPU Functional Description
        1. 3.7.2.1 FPU Views of the Register Bank
        2. 3.7.2.2 Modes of Operation
          1. 3.7.2.2.1 Full-Compliance Mode
          2. 3.7.2.2.2 Flush-to-Zero Mode
          3. 3.7.2.2.3 Default NaN Mode
        3. 3.7.2.3 FPU Instruction Set
        4. 3.7.2.4 Compliance With the IEEE 754 Standard
        5. 3.7.2.5 Complete Implementation of the IEEE 754 Standard
        6. 3.7.2.6 IEEE 754 Standard Implementation Choices
          1. 3.7.2.6.1 NaN Handling
          2. 3.7.2.6.2 Comparisons
          3. 3.7.2.6.3 Underflow
        7. 3.7.2.7 Exceptions
      3. 3.7.3 FPU Programmers Model
        1. 3.7.3.1 Enabling the FPU
          1. 3.7.3.1.1 Enabling the FPU
    8. 3.8 Memory Protection Unit (MPU)
      1. 3.8.1 About the MPU
      2. 3.8.2 MPU Functional Description
      3. 3.8.3 MPU Programmers Model
    9. 3.9 Arm® Cortex®-M4F Processor Registers
      1. 3.9.1 CPU_DWT Registers
      2. 3.9.2 CPU_FPB Registers
      3. 3.9.3 CPU_ITM Registers
      4. 3.9.4 CPU_SCS Registers
      5. 3.9.5 CPU_TPIU Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Arm® Cortex®-M4F Peripherals
    1. 5.1 Arm® Cortex®-M4F Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  7. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  8. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  9. 8 Power, Reset, and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 DDI_0_OSC Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  10. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  11. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM_MMR Registers
      2. 10.7.2 SRAM Registers
  12. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  13. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  14. 13Cryptography
    1. 13.1 AES and Hash Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master PROT Enable
          1. 13.5.4.2.1 Master PROT-Privileged Access-Enable
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
        5. 13.5.6.5 Hash Engine
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Hashing
        1. 13.7.3.1 Data Format and Byte Order
        2. 13.7.3.2 Basic Hash With Data From DMA
          1. 13.7.3.2.1 New Hash Session With Digest Read Through Slave
          2. 13.7.3.2.2 New Hash Session With Digest to External Memory
          3. 13.7.3.2.3 Resumed Hash Session
        3. 13.7.3.3 HMAC
          1. 13.7.3.3.1 Secure HMAC
        4. 13.7.3.4 Alternative Basic Hash Where Data Originates From Slave Interface
          1. 13.7.3.4.1 New Hash Session
          2. 13.7.3.4.2 Resumed Hash Session
      4. 13.7.4 Encryption and Decryption
        1. 13.7.4.1 Data Format and Byte Order
        2. 13.7.4.2 Key Store
          1. 13.7.4.2.1 Load Keys From External Memory
        3. 13.7.4.3 Basic AES Modes
          1. 13.7.4.3.1 AES-ECB
          2. 13.7.4.3.2 AES-CBC
          3. 13.7.4.3.3 AES-CTR
          4. 13.7.4.3.4 Programming Sequence With DMA Data
        4. 13.7.4.4 CBC-MAC
          1. 13.7.4.4.1 Programming Sequence for CBC-MAC
        5. 13.7.4.5 AES-CCM
          1. 13.7.4.5.1 Programming Sequence for AES-CCM
        6. 13.7.4.6 AES-GCM
          1. 13.7.4.6.1 Programming Sequence for AES-GCM
      5. 13.7.5 Exceptions Handling
        1. 13.7.5.1 Soft Reset
        2. 13.7.5.2 External Port Errors
        3. 13.7.5.3 Key Store Errors
          1. 13.7.5.3.1 PKA Engine
          2. 13.7.5.3.2 Functional Description
            1. 13.7.5.3.2.1 Module Architecture
          3. 13.7.5.3.3 PKA RAM
            1. 13.7.5.3.3.1 PKCP Operations
            2. 13.7.5.3.3.2 Sequencer Operations
              1. 13.7.5.3.3.2.1 Modular Exponentiation Operations
              2. 13.7.5.3.3.2.2 Modular Inversion Operation
              3. 13.7.5.3.3.2.3 Performance
              4. 13.7.5.3.3.2.4 ECC Operations
              5. 13.7.5.3.3.2.5 Performance
              6. 13.7.5.3.3.2.6 ExpMod Performance
              7. 13.7.5.3.3.2.7 Modular Inversion Performance
              8. 13.7.5.3.3.2.8 ECC Operation Performance
            3. 13.7.5.3.3.3 Sequencer ROM Behavior and Interfaces
            4. 13.7.5.3.3.4 Register Configurations
            5. 13.7.5.3.3.5 Operation Sequence
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  15. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 UDMA Registers
  17. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  18. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  19. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  20. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 AIODIO
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 SMPH
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPIM
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
              1. 20.4.7.2.5.1.1 Timer Period and Pulse Width Capture
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.2.1 Center-Aligned PWM Generation by Channel 0
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.3.1 Edge-Aligned PWM Generation by Channel 0
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 COMPA
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 COMPB
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference DAC
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 ISRC
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  24. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

8.8.2 PRCM Registers

Table 8-27 lists the memory-mapped registers for the PRCM registers. All register offset addresses not listed in Table 8-27 should be considered as reserved locations and the register contents should not be modified.

Table 8-27 PRCM Registers
OffsetAcronymRegister NameSection
0hINFRCLKDIVRInfrastructure Clock Division Factor For Run ModeINFRCLKDIVR Register (Offset = 0h) [Reset = 00000000h]
4hINFRCLKDIVSInfrastructure Clock Division Factor For Sleep ModeINFRCLKDIVS Register (Offset = 4h) [Reset = 00000000h]
8hINFRCLKDIVDSInfrastructure Clock Division Factor For DeepSleep ModeINFRCLKDIVDS Register (Offset = 8h) [Reset = 00000000h]
ChVDCTLMCU Voltage Domain ControlVDCTL Register (Offset = Ch) [Reset = 00000000h]
28hCLKLOADCTLLoad PRCM Settings To CLKCTRL Power DomainCLKLOADCTL Register (Offset = 28h) [Reset = 00000002h]
2ChRFCCLKGRFC Clock GateRFCCLKG Register (Offset = 2Ch) [Reset = 00000001h]
30hVIMSCLKGVIMS Clock GateVIMSCLKG Register (Offset = 30h) [Reset = 00000003h]
3ChSECDMACLKGRSEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All ModesSECDMACLKGR Register (Offset = 3Ch) [Reset = 00000000h]
40hSECDMACLKGSSEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep ModeSECDMACLKGS Register (Offset = 40h) [Reset = 00000000h]
44hSECDMACLKGDSSEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep ModeSECDMACLKGDS Register (Offset = 44h) [Reset = 00000000h]
48hGPIOCLKGRGPIO Clock Gate For Run And All ModesGPIOCLKGR Register (Offset = 48h) [Reset = 00000000h]
4ChGPIOCLKGSGPIO Clock Gate For Sleep ModeGPIOCLKGS Register (Offset = 4Ch) [Reset = 00000000h]
50hGPIOCLKGDSGPIO Clock Gate For Deep Sleep ModeGPIOCLKGDS Register (Offset = 50h) [Reset = 00000000h]
54hGPTCLKGRGPT Clock Gate For Run And All ModesGPTCLKGR Register (Offset = 54h) [Reset = 00000000h]
58hGPTCLKGSGPT Clock Gate For Sleep ModeGPTCLKGS Register (Offset = 58h) [Reset = 00000000h]
5ChGPTCLKGDSGPT Clock Gate For Deep Sleep ModeGPTCLKGDS Register (Offset = 5Ch) [Reset = 00000000h]
60hI2CCLKGRI2C Clock Gate For Run And All ModesI2CCLKGR Register (Offset = 60h) [Reset = 00000000h]
64hI2CCLKGSI2C Clock Gate For Sleep ModeI2CCLKGS Register (Offset = 64h) [Reset = 00000000h]
68hI2CCLKGDSI2C Clock Gate For Deep Sleep ModeI2CCLKGDS Register (Offset = 68h) [Reset = 00000000h]
6ChUARTCLKGRUART Clock Gate For Run And All ModesUARTCLKGR Register (Offset = 6Ch) [Reset = 00000000h]
70hUARTCLKGSUART Clock Gate For Sleep ModeUARTCLKGS Register (Offset = 70h) [Reset = 00000000h]
74hUARTCLKGDSUART Clock Gate For Deep Sleep ModeUARTCLKGDS Register (Offset = 74h) [Reset = 00000000h]
78hSSICLKGRSSI Clock Gate For Run And All ModesSSICLKGR Register (Offset = 78h) [Reset = 00000000h]
7ChSSICLKGSSSI Clock Gate For Sleep ModeSSICLKGS Register (Offset = 7Ch) [Reset = 00000000h]
80hSSICLKGDSSSI Clock Gate For Deep Sleep ModeSSICLKGDS Register (Offset = 80h) [Reset = 00000000h]
84hI2SCLKGRI2S Clock Gate For Run And All ModesI2SCLKGR Register (Offset = 84h) [Reset = 00000000h]
88hI2SCLKGSI2S Clock Gate For Sleep ModeI2SCLKGS Register (Offset = 88h) [Reset = 00000000h]
8ChI2SCLKGDSI2S Clock Gate For Deep Sleep ModeI2SCLKGDS Register (Offset = 8Ch) [Reset = 00000000h]
B4hSYSBUSCLKDIVInternalSYSBUSCLKDIV Register (Offset = B4h) [Reset = 00000000h]
B8hCPUCLKDIVInternalCPUCLKDIV Register (Offset = B8h) [Reset = 00000000h]
BChPERBUSCPUCLKDIVInternalPERBUSCPUCLKDIV Register (Offset = BCh) [Reset = 00000000h]
C4hPERDMACLKDIVInternalPERDMACLKDIV Register (Offset = C4h) [Reset = 00000000h]
C8hI2SBCLKSELI2S Clock ControlI2SBCLKSEL Register (Offset = C8h) [Reset = 00000000h]
CChGPTCLKDIVGPT ScalarGPTCLKDIV Register (Offset = CCh) [Reset = 00000000h]
D0hI2SCLKCTLI2S Clock ControlI2SCLKCTL Register (Offset = D0h) [Reset = 00000000h]
D4hI2SMCLKDIVMCLK Division RatioI2SMCLKDIV Register (Offset = D4h) [Reset = 00000000h]
D8hI2SBCLKDIVBCLK Division RatioI2SBCLKDIV Register (Offset = D8h) [Reset = 00000000h]
DChI2SWCLKDIVWCLK Division RatioI2SWCLKDIV Register (Offset = DCh) [Reset = 00000000h]
F0hRESETSECDMARESET For SEC (PKA And TRNG And CRYPTO) And UDMARESETSECDMA Register (Offset = F0h) [Reset = 00000000h]
F4hRESETGPIORESET For GPIO IPsRESETGPIO Register (Offset = F4h) [Reset = 00000000h]
F8hRESETGPTRESET For GPT IpsRESETGPT Register (Offset = F8h) [Reset = 00000000h]
FChRESETI2CRESET For I2C IPsRESETI2C Register (Offset = FCh) [Reset = 00000000h]
100hRESETUARTRESET For UART IPsRESETUART Register (Offset = 100h) [Reset = 00000000h]
104hRESETSSIRESET For SSI IPsRESETSSI Register (Offset = 104h) [Reset = 00000000h]
108hRESETI2SRESET For I2S IPRESETI2S Register (Offset = 108h) [Reset = 00000000h]
12ChPDCTL0Power Domain ControlPDCTL0 Register (Offset = 12Ch) [Reset = 00000000h]
130hPDCTL0RFCRFC Power Domain ControlPDCTL0RFC Register (Offset = 130h) [Reset = 00000000h]
134hPDCTL0SERIALSERIAL Power Domain ControlPDCTL0SERIAL Register (Offset = 134h) [Reset = 00000000h]
138hPDCTL0PERIPHPERIPH Power Domain ControlPDCTL0PERIPH Register (Offset = 138h) [Reset = 00000000h]
140hPDSTAT0Power Domain StatusPDSTAT0 Register (Offset = 140h) [Reset = 00000000h]
144hPDSTAT0RFCRFC Power Domain StatusPDSTAT0RFC Register (Offset = 144h) [Reset = 00000000h]
148hPDSTAT0SERIALSERIAL Power Domain StatusPDSTAT0SERIAL Register (Offset = 148h) [Reset = 00000000h]
14ChPDSTAT0PERIPHPERIPH Power Domain StatusPDSTAT0PERIPH Register (Offset = 14Ch) [Reset = 00000000h]
17ChPDCTL1Power Domain ControlPDCTL1 Register (Offset = 17Ch) [Reset = 0000000Ah]
184hPDCTL1CPUCPU Power Domain Direct ControlPDCTL1CPU Register (Offset = 184h) [Reset = 00000001h]
188hPDCTL1RFCRFC Power Domain Direct ControlPDCTL1RFC Register (Offset = 188h) [Reset = 00000000h]
18ChPDCTL1VIMSVIMS Mode Direct ControlPDCTL1VIMS Register (Offset = 18Ch) [Reset = 00000001h]
194hPDSTAT1Power Manager StatusPDSTAT1 Register (Offset = 194h) [Reset = 0000001Ah]
198hPDSTAT1BUSBUS Power Domain Direct Read StatusPDSTAT1BUS Register (Offset = 198h) [Reset = 00000001h]
19ChPDSTAT1RFCRFC Power Domain Direct Read StatusPDSTAT1RFC Register (Offset = 19Ch) [Reset = 00000000h]
1A0hPDSTAT1CPUCPU Power Domain Direct Read StatusPDSTAT1CPU Register (Offset = 1A0h) [Reset = 00000001h]
1A4hPDSTAT1VIMSVIMS Mode Direct Read StatusPDSTAT1VIMS Register (Offset = 1A4h) [Reset = 00000001h]
1CChRFCBITSControl To RFCRFCBITS Register (Offset = 1CCh) [Reset = 00000000h]
1D0hRFCMODESELSelected RFC ModeRFCMODESEL Register (Offset = 1D0h) [Reset = 00000000h]
1D4hRFCMODEHWOPTAllowed RFC ModesRFCMODEHWOPT Register (Offset = 1D4h) [Reset = 00000000h]
1E0hPWRPROFSTATPower Profiler RegisterPWRPROFSTAT Register (Offset = 1E0h) [Reset = 00000001h]
21ChMCUSRAMCFGMCU SRAM configurationMCUSRAMCFG Register (Offset = 21Ch) [Reset = 00000020h]
224hRAMRETENMemory Retention ControlRAMRETEN Register (Offset = 224h) [Reset = 0000000Bh]
290hOSCIMSCOscillator Interrupt Mask ControlOSCIMSC Register (Offset = 290h) [Reset = 00000036h]
294hOSCRISOscillator Raw Interrupt StatusOSCRIS Register (Offset = 294h) [Reset = 00000000h]
298hOSCICROscillator Raw Interrupt ClearOSCICR Register (Offset = 298h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Table 8-28 shows the codes that are used for access types in this section.

Table 8-28 PRCM Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.8.2.1 INFRCLKDIVR Register (Offset = 0h) [Reset = 00000000h]

INFRCLKDIVR is shown in Figure 8-24 and described in Table 8-29.

Return to the Summary Table.

Infrastructure Clock Division Factor For Run Mode

Figure 8-24 INFRCLKDIVR Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRATIO
R-0hR/W-0h
Table 8-29 INFRCLKDIVR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0RATIOR/W0hDivision rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode. Division ratio affects both infrastructure clock and perbusull clock.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 8
3h = Divide by 32

8.8.2.2 INFRCLKDIVS Register (Offset = 4h) [Reset = 00000000h]

INFRCLKDIVS is shown in Figure 8-25 and described in Table 8-30.

Return to the Summary Table.

Infrastructure Clock Division Factor For Sleep Mode

Figure 8-25 INFRCLKDIVS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRATIO
R-0hR/W-0h
Table 8-30 INFRCLKDIVS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0RATIOR/W0hDivision rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode. Division ratio affects both infrastructure clock and perbusull clock.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 8
3h = Divide by 32

8.8.2.3 INFRCLKDIVDS Register (Offset = 8h) [Reset = 00000000h]

INFRCLKDIVDS is shown in Figure 8-26 and described in Table 8-31.

Return to the Summary Table.

Infrastructure Clock Division Factor For DeepSleep Mode

Figure 8-26 INFRCLKDIVDS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRATIO
R-0hR/W-0h
Table 8-31 INFRCLKDIVDS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0RATIOR/W0hDivision rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode. Division ratio affects both infrastructure clock and perbusull clock.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 8
3h = Divide by 32

8.8.2.4 VDCTL Register (Offset = Ch) [Reset = 00000000h]

VDCTL is shown in Figure 8-27 and described in Table 8-32.

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MCU Voltage Domain Control

Figure 8-27 VDCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDULDO
R-0hR/W-0h
Table 8-32 VDCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ULDOR/W0hRequest PMCTL to switch to uLDO.
0: No request
1: Assert request when possible
The bit will have no effect before the following requirements are met:
1. PDCTL1.CPU_ON = 0
2. PDCTL1.VIMS_MODE = x0
3. SECDMACLKGDS.DMA_CLK_EN = 0 and SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD)
4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD)
5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD)
6. RFC do no request access to BUS
7. System CPU in deepsleep

8.8.2.5 CLKLOADCTL Register (Offset = 28h) [Reset = 00000002h]

CLKLOADCTL is shown in Figure 8-28 and described in Table 8-33.

Return to the Summary Table.

Load PRCM Settings To CLKCTRL Power Domain

Figure 8-28 CLKLOADCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLOAD_DONELOAD
R-0hR-1hW-0h
Table 8-33 CLKLOADCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1LOAD_DONER1hStatus of LOAD.
Will be cleared to 0 when any of the registers requiring a LOAD is written to, and be set to 1 when a LOAD is done.
Note that writing no change to a register will result in the LOAD_DONE being cleared.
0 : One or more registers have been write accessed after last LOAD
1 : No registers are write accessed after last LOAD
0LOADW0h
0: No action
1: Load settings to CLKCTRL. Bit is HW cleared.
Multiple changes to settings may be done before LOAD is written once so all changes takes place at the same time. LOAD can also be done after single setting updates.
Registers that needs to be followed by LOAD before settings being applied are:
- SYSBUSCLKDIV
- CPUCLKDIV
- PERBUSCPUCLKDIV
- PERDMACLKDIV
- PERBUSCPUCLKG
- RFCCLKG
- VIMSCLKG
- SECDMACLKGR
- SECDMACLKGS
- SECDMACLKGDS
- GPIOCLKGR
- GPIOCLKGS
- GPIOCLKGDS
- GPTCLKGR
- GPTCLKGS
- GPTCLKGDS
- GPTCLKDIV
- I2CCLKGR
- I2CCLKGS
- I2CCLKGDS
- SSICLKGR
- SSICLKGS
- SSICLKGDS
- UARTCLKGR
- UARTCLKGS
- UARTCLKGDS
- I2SCLKGR
- I2SCLKGS
- I2SCLKGDS
- I2SBCLKSEL
- I2SCLKCTL
- I2SMCLKDIV
- I2SBCLKDIV
- I2SWCLKDIV

8.8.2.6 RFCCLKG Register (Offset = 2Ch) [Reset = 00000001h]

RFCCLKG is shown in Figure 8-29 and described in Table 8-34.

Return to the Summary Table.

RFC Clock Gate

Figure 8-29 RFCCLKG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_EN
R-0hR/W-1h
Table 8-34 RFCCLKG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0CLK_ENR/W1h
0: Disable Clock
1: Enable clock if RFC power domain is on
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.7 VIMSCLKG Register (Offset = 30h) [Reset = 00000003h]

VIMSCLKG is shown in Figure 8-30 and described in Table 8-35.

Return to the Summary Table.

VIMS Clock Gate

Figure 8-30 VIMSCLKG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCLK_EN
R-0hR/W-3h
Table 8-35 VIMSCLKG Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0CLK_ENR/W3h00: Disable clock
01: Disable clock when SYSBUS clock is disabled
11: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.8 SECDMACLKGR Register (Offset = 3Ch) [Reset = 00000000h]

SECDMACLKGR is shown in Figure 8-31 and described in Table 8-36.

Return to the Summary Table.

SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes

Figure 8-31 SECDMACLKGR Register
3130292827262524
RESERVEDDMA_AM_CLK_EN
R-0hR/W-0h
2322212019181716
RESERVEDPKA_ZERIOZE_RESET_NPKA_AM_CLK_ENTRNG_AM_CLK_ENCRYPTO_AM_CLK_EN
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDDMA_CLK_EN
R-0hR/W-0h
76543210
RESERVEDPKA_CLK_ENTRNG_CLK_ENCRYPTO_CLK_EN
R-0hR/W-0hR/W-0hR/W-0h
Table 8-36 SECDMACLKGR Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DMA_AM_CLK_ENR/W0h
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)
Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN when enabled.
SYSBUS clock will always run when enabled
For changes to take effect, CLKLOADCTL.LOAD needs to be written
23-20RESERVEDR0hReserved
19PKA_ZERIOZE_RESET_NR/W0hZeroization logic hardware reset.
0: pka_zeroize logic inactive.
1: pka_zeroize of memory is enabled.
This register must remain active until the memory are completely zeroized which requires 256 periods on systembus clock.
18PKA_AM_CLK_ENR/W0h
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)
Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN when enabled.
For changes to take effect, CLKLOADCTL.LOAD needs to be written
17TRNG_AM_CLK_ENR/W0h
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)
Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN when enabled.
For changes to take effect, CLKLOADCTL.LOAD needs to be written
16CRYPTO_AM_CLK_ENR/W0h
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)
Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and SECDMACLKGDS.CRYPTO_CLK_EN when enabled.
SYSBUS clock will always run when enabled
For changes to take effect, CLKLOADCTL.LOAD needs to be written
15-9RESERVEDR0hReserved
8DMA_CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by DMA_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-3RESERVEDR0hReserved
2PKA_CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by PKA_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1TRNG_CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by TRNG_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
0CRYPTO_CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by CRYPTO_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.9 SECDMACLKGS Register (Offset = 40h) [Reset = 00000000h]

SECDMACLKGS is shown in Figure 8-32 and described in Table 8-37.

Return to the Summary Table.

SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode

Figure 8-32 SECDMACLKGS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDMA_CLK_EN
R-0hR/W-0h
76543210
RESERVEDPKA_CLK_ENTRNG_CLK_ENCRYPTO_CLK_EN
R-0hR/W-0hR/W-0hR/W-0h
Table 8-37 SECDMACLKGS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMA_CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-3RESERVEDR0hReserved
2PKA_CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1TRNG_CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
0CRYPTO_CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.10 SECDMACLKGDS Register (Offset = 44h) [Reset = 00000000h]

SECDMACLKGDS is shown in Figure 8-33 and described in Table 8-38.

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SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode

Figure 8-33 SECDMACLKGDS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDMA_CLK_EN
R-0hR/W-0h
76543210
RESERVEDPKA_CLK_ENTRNG_CLK_ENCRYPTO_CLK_EN
R-0hR/W-0hR/W-0hR/W-0h
Table 8-38 SECDMACLKGDS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMA_CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-3RESERVEDR0hReserved
2PKA_CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1TRNG_CLK_ENR/W0h
0: Disable clock
1: Enable clock
SYSBUS clock will always run when enabled
Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
0CRYPTO_CLK_ENR/W0h
0: Disable clock
1: Enable clock
SYSBUS clock will always run when enabled
Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.11 GPIOCLKGR Register (Offset = 48h) [Reset = 00000000h]

GPIOCLKGR is shown in Figure 8-34 and described in Table 8-39.

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GPIO Clock Gate For Run And All Modes

Figure 8-34 GPIOCLKGR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAM_CLK_EN
R-0hR/W-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-39 GPIOCLKGR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8AM_CLK_ENR/W0h
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)
Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled.
For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-1RESERVEDR0hReserved
0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.12 GPIOCLKGS Register (Offset = 4Ch) [Reset = 00000000h]

GPIOCLKGS is shown in Figure 8-35 and described in Table 8-40.

Return to the Summary Table.

GPIO Clock Gate For Sleep Mode

Figure 8-35 GPIOCLKGS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-40 GPIOCLKGS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by GPIOCLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.13 GPIOCLKGDS Register (Offset = 50h) [Reset = 00000000h]

GPIOCLKGDS is shown in Figure 8-36 and described in Table 8-41.

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GPIO Clock Gate For Deep Sleep Mode

Figure 8-36 GPIOCLKGDS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-41 GPIOCLKGDS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by GPIOCLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.14 GPTCLKGR Register (Offset = 54h) [Reset = 00000000h]

GPTCLKGR is shown in Figure 8-37 and described in Table 8-42.

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GPT Clock Gate For Run And All Modes

Figure 8-37 GPTCLKGR Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDAM_CLK_ENRESERVEDCLK_EN
R-0hR/W-0hR-0hR/W-0h
Table 8-42 GPTCLKGR Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-8AM_CLK_ENR/W0hEach bit below has the following meaning:
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)
Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled.
ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for GPT0 in all modes
2h = Enable clock for GPT1 in all modes
4h = Enable clock for GPT2 in all modes
8h = Enable clock for GPT3 in all modes
7-4RESERVEDR0hReserved
3-0CLK_ENR/W0hEach bit below has the following meaning:
0: Disable clock
1: Enable clock
Can be forced on by AM_CLK_EN
ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for GPT0
2h = Enable clock for GPT1
4h = Enable clock for GPT2
8h = Enable clock for GPT3

8.8.2.15 GPTCLKGS Register (Offset = 58h) [Reset = 00000000h]

GPTCLKGS is shown in Figure 8-38 and described in Table 8-43.

Return to the Summary Table.

GPT Clock Gate For Sleep Mode

Figure 8-38 GPTCLKGS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-43 GPTCLKGS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0CLK_ENR/W0hEach bit below has the following meaning:
0: Disable clock
1: Enable clock
Can be forced on by GPTCLKGR.AM_CLK_EN
ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for GPT0
2h = Enable clock for GPT1
4h = Enable clock for GPT2
8h = Enable clock for GPT3

8.8.2.16 GPTCLKGDS Register (Offset = 5Ch) [Reset = 00000000h]

GPTCLKGDS is shown in Figure 8-39 and described in Table 8-44.

Return to the Summary Table.

GPT Clock Gate For Deep Sleep Mode

Figure 8-39 GPTCLKGDS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-44 GPTCLKGDS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0CLK_ENR/W0hEach bit below has the following meaning:
0: Disable clock
1: Enable clock
Can be forced on by GPTCLKGR.AM_CLK_EN
ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for GPT0
2h = Enable clock for GPT1
4h = Enable clock for GPT2
8h = Enable clock for GPT3

8.8.2.17 I2CCLKGR Register (Offset = 60h) [Reset = 00000000h]

I2CCLKGR is shown in Figure 8-40 and described in Table 8-45.

Return to the Summary Table.

I2C Clock Gate For Run And All Modes

Figure 8-40 I2CCLKGR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAM_CLK_EN
R-0hR/W-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-45 I2CCLKGR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8AM_CLK_ENR/W0h
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)
Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled.
For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-1RESERVEDR0hReserved
0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.18 I2CCLKGS Register (Offset = 64h) [Reset = 00000000h]

I2CCLKGS is shown in Figure 8-41 and described in Table 8-46.

Return to the Summary Table.

I2C Clock Gate For Sleep Mode

Figure 8-41 I2CCLKGS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-46 I2CCLKGS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by I2CCLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.19 I2CCLKGDS Register (Offset = 68h) [Reset = 00000000h]

I2CCLKGDS is shown in Figure 8-42 and described in Table 8-47.

Return to the Summary Table.

I2C Clock Gate For Deep Sleep Mode

Figure 8-42 I2CCLKGDS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-47 I2CCLKGDS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by I2CCLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.20 UARTCLKGR Register (Offset = 6Ch) [Reset = 00000000h]

UARTCLKGR is shown in Figure 8-43 and described in Table 8-48.

Return to the Summary Table.

UART Clock Gate For Run And All Modes

Figure 8-43 UARTCLKGR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAM_CLK_EN
R-0hR/W-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-48 UARTCLKGR Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-8AM_CLK_ENR/W0h
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)
Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled.
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for UART0
2h = Enable clock for UART1
7-2RESERVEDR0hReserved
1-0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for UART0
2h = Enable clock for UART1

8.8.2.21 UARTCLKGS Register (Offset = 70h) [Reset = 00000000h]

UARTCLKGS is shown in Figure 8-44 and described in Table 8-49.

Return to the Summary Table.

UART Clock Gate For Sleep Mode

Figure 8-44 UARTCLKGS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-49 UARTCLKGS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by UARTCLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for UART0
2h = Enable clock for UART1

8.8.2.22 UARTCLKGDS Register (Offset = 74h) [Reset = 00000000h]

UARTCLKGDS is shown in Figure 8-45 and described in Table 8-50.

Return to the Summary Table.

UART Clock Gate For Deep Sleep Mode

Figure 8-45 UARTCLKGDS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-50 UARTCLKGDS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by UARTCLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for UART0
2h = Enable clock for UART1

8.8.2.23 SSICLKGR Register (Offset = 78h) [Reset = 00000000h]

SSICLKGR is shown in Figure 8-46 and described in Table 8-51.

Return to the Summary Table.

SSI Clock Gate For Run And All Modes

Figure 8-46 SSICLKGR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAM_CLK_EN
R-0hR/W-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-51 SSICLKGR Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-8AM_CLK_ENR/W0h
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)
Overrides CLK_EN, SSICLKGS.CLK_EN and SSICLKGDS.CLK_EN when enabled.
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for SSI0
2h = Enable clock for SSI1
7-2RESERVEDR0hReserved
1-0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for SSI0
2h = Enable clock for SSI1

8.8.2.24 SSICLKGS Register (Offset = 7Ch) [Reset = 00000000h]

SSICLKGS is shown in Figure 8-47 and described in Table 8-52.

Return to the Summary Table.

SSI Clock Gate For Sleep Mode

Figure 8-47 SSICLKGS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-52 SSICLKGS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by SSICLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for SSI0
2h = Enable clock for SSI1

8.8.2.25 SSICLKGDS Register (Offset = 80h) [Reset = 00000000h]

SSICLKGDS is shown in Figure 8-48 and described in Table 8-53.

Return to the Summary Table.

SSI Clock Gate For Deep Sleep Mode

Figure 8-48 SSICLKGDS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-53 SSICLKGDS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by SSICLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for SSI0
2h = Enable clock for SSI1

8.8.2.26 I2SCLKGR Register (Offset = 84h) [Reset = 00000000h]

I2SCLKGR is shown in Figure 8-49 and described in Table 8-54.

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I2S Clock Gate For Run And All Modes

Figure 8-49 I2SCLKGR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAM_CLK_EN
R-0hR/W-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-54 I2SCLKGR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8AM_CLK_ENR/W0h
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)
Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled.
SYSBUS clock will always run when enabled
For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-1RESERVEDR0hReserved
0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.27 I2SCLKGS Register (Offset = 88h) [Reset = 00000000h]

I2SCLKGS is shown in Figure 8-50 and described in Table 8-55.

Return to the Summary Table.

I2S Clock Gate For Sleep Mode

Figure 8-50 I2SCLKGS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-55 I2SCLKGS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0CLK_ENR/W0h
0: Disable clock
1: Enable clock
Can be forced on by I2SCLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.28 I2SCLKGDS Register (Offset = 8Ch) [Reset = 00000000h]

I2SCLKGDS is shown in Figure 8-51 and described in Table 8-56.

Return to the Summary Table.

I2S Clock Gate For Deep Sleep Mode

Figure 8-51 I2SCLKGDS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_EN
R-0hR/W-0h
Table 8-56 I2SCLKGDS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0CLK_ENR/W0h
0: Disable clock
1: Enable clock
SYSBUS clock will always run when enabled
Can be forced on by I2SCLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.29 SYSBUSCLKDIV Register (Offset = B4h) [Reset = 00000000h]

SYSBUSCLKDIV is shown in Figure 8-52 and described in Table 8-57.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 8-52 SYSBUSCLKDIV Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRATIO
R-0hR/W-0h
Table 8-57 SYSBUSCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0RATIOR/W0hInternal. Only to be used through TI provided API.

8.8.2.30 CPUCLKDIV Register (Offset = B8h) [Reset = 00000000h]

CPUCLKDIV is shown in Figure 8-53 and described in Table 8-58.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 8-53 CPUCLKDIV Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRATIO
R-0hR/W-0h
Table 8-58 CPUCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0RATIOR/W0hInternal. Only to be used through TI provided API.

8.8.2.31 PERBUSCPUCLKDIV Register (Offset = BCh) [Reset = 00000000h]

PERBUSCPUCLKDIV is shown in Figure 8-54 and described in Table 8-59.

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Internal. Only to be used through TI provided API.

Figure 8-54 PERBUSCPUCLKDIV Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRATIO
R-0hR/W-0h
Table 8-59 PERBUSCPUCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0RATIOR/W0hInternal. Only to be used through TI provided API.

8.8.2.32 PERDMACLKDIV Register (Offset = C4h) [Reset = 00000000h]

PERDMACLKDIV is shown in Figure 8-55 and described in Table 8-60.

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Internal. Only to be used through TI provided API.

Figure 8-55 PERDMACLKDIV Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRATIO
R-0hR/W-0h
Table 8-60 PERDMACLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0RATIOR/W0hInternal. Only to be used through TI provided API.

8.8.2.33 I2SBCLKSEL Register (Offset = C8h) [Reset = 00000000h]

I2SBCLKSEL is shown in Figure 8-56 and described in Table 8-61.

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I2S Clock Control

Figure 8-56 I2SBCLKSEL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 8-61 I2SBCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0SRCR/W0hBCLK source selector
0: Use external BCLK
1: Use internally generated clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.34 GPTCLKDIV Register (Offset = CCh) [Reset = 00000000h]

GPTCLKDIV is shown in Figure 8-57 and described in Table 8-62.

Return to the Summary Table.

GPT Scalar

Figure 8-57 GPTCLKDIV Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRATIO
R-0hR/W-0h
Table 8-62 GPTCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0RATIOR/W0hScalar used for GPTs. The division rate will be constant and ungated for Run / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD needs to be written Other values are not supported.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 4
3h = Divide by 8
4h = Divide by 16
5h = Divide by 32
6h = Divide by 64
7h = Divide by 128
8h = Divide by 256

8.8.2.35 I2SCLKCTL Register (Offset = D0h) [Reset = 00000000h]

I2SCLKCTL is shown in Figure 8-58 and described in Table 8-63.

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I2S Clock Control

Figure 8-58 I2SCLKCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSMPL_ON_POSEDGEWCLK_PHASEEN
R-0hR/W-0hR/W-0hR/W-0h
Table 8-63 I2SCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3SMPL_ON_POSEDGER/W0hOn the I2S serial interface, data and WCLK is sampled and clocked out on opposite edges of BCLK.
0 - data and WCLK are sampled on the negative edge and clocked out on the positive edge.
1 - data and WCLK are sampled on the positive edge and clocked out on the negative edge.
For changes to take effect, CLKLOADCTL.LOAD needs to be written
2-1WCLK_PHASER/W0hDecides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV).
0: Single phase
1: Dual phase
2: User Defined
3: Reserved/Undefined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
0ENR/W0h
0: MCLK, BCLK and WCLK will be static low
1: Enables the generation of MCLK, BCLK and WCLK
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.36 I2SMCLKDIV Register (Offset = D4h) [Reset = 00000000h]

I2SMCLKDIV is shown in Figure 8-59 and described in Table 8-64.

Return to the Summary Table.

MCLK Division Ratio

Figure 8-59 I2SMCLKDIV Register
313029282726252423222120191817161514131211109876543210
RESERVEDMDIV
R-0hR/W-0h
Table 8-64 I2SMCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0MDIVR/W0hAn unsigned factor of the division ratio used to generate MCLK [2-1024]:
MCLK = MCUCLK/MDIV[Hz]
MCUCLK is 48MHz.
A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If MDIV is odd the low phase of the clock is one MCUCLK period longer than the high phase.
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.37 I2SBCLKDIV Register (Offset = D8h) [Reset = 00000000h]

I2SBCLKDIV is shown in Figure 8-60 and described in Table 8-65.

Return to the Summary Table.

BCLK Division Ratio

Figure 8-60 I2SBCLKDIV Register
313029282726252423222120191817161514131211109876543210
RESERVEDBDIV
R-0hR/W-0h
Table 8-65 I2SBCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0BDIVR/W0hAn unsigned factor of the division ratio used to generate I2S BCLK [2-1024]:
BCLK = MCUCLK/BDIV[Hz]
MCUCLK is 48MHz.
A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock is one MCUCLK period longer than the high phase.
If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the clock is one MCUCLK period longer than the low phase.
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.38 I2SWCLKDIV Register (Offset = DCh) [Reset = 00000000h]

I2SWCLKDIV is shown in Figure 8-61 and described in Table 8-66.

Return to the Summary Table.

WCLK Division Ratio

Figure 8-61 I2SWCLKDIV Register
313029282726252423222120191817161514131211109876543210
RESERVEDWDIV
R-0hR/W-0h
Table 8-66 I2SWCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0WDIVR/W0hIf I2SCLKCTL.WCLK_PHASE = 0, Single phase.
WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK periods.

WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz]
MCUCLK is 48MHz.
If I2SCLKCTL.WCLK_PHASE = 1, Dual phase.
Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK periods.
WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz]
If I2SCLKCTL.WCLK_PHASE = 2, User defined.
WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] (unsigned, [1-255]) BCLK periods.
WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]
For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.39 RESETSECDMA Register (Offset = F0h) [Reset = 00000000h]

RESETSECDMA is shown in Figure 8-62 and described in Table 8-67.

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RESET For SEC (PKA And TRNG And CRYPTO) And UDMA

Figure 8-62 RESETSECDMA Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDMA
R-0hW-0h
76543210
RESERVEDPKATRNGCRYPTO
R-0hW-0hW-0hW-0h
Table 8-67 RESETSECDMA Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMAW0hWrite 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.
7-3RESERVEDR0hReserved
2PKAW0hWrite 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.
1TRNGW0hWrite 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.
0CRYPTOW0hWrite 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.40 RESETGPIO Register (Offset = F4h) [Reset = 00000000h]

RESETGPIO is shown in Figure 8-63 and described in Table 8-68.

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RESET For GPIO IPs

Figure 8-63 RESETGPIO Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDGPIO
R-0hW-0h
Table 8-68 RESETGPIO Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0GPIOW0h
0: No action
1: Reset GPIO. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.41 RESETGPT Register (Offset = F8h) [Reset = 00000000h]

RESETGPT is shown in Figure 8-64 and described in Table 8-69.

Return to the Summary Table.

RESET For GPT Ips

Figure 8-64 RESETGPT Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDGPT
R-0hW-0h
Table 8-69 RESETGPT Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0GPTW0h
0: No action
1: Reset all GPTs. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.42 RESETI2C Register (Offset = FCh) [Reset = 00000000h]

RESETI2C is shown in Figure 8-65 and described in Table 8-70.

Return to the Summary Table.

RESET For I2C IPs

Figure 8-65 RESETI2C Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDI2C
R-0hW-0h
Table 8-70 RESETI2C Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0I2CW0h
0: No action
1: Reset I2C. HW cleared.
Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.43 RESETUART Register (Offset = 100h) [Reset = 00000000h]

RESETUART is shown in Figure 8-66 and described in Table 8-71.

Return to the Summary Table.

RESET For UART IPs

Figure 8-66 RESETUART Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDUART1UART0
R-0hW-0hW-0h
Table 8-71 RESETUART Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1UART1W0h
0: No action
1: Reset UART1. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.
0UART0W0h
0: No action
1: Reset UART0. HW cleared.
Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.44 RESETSSI Register (Offset = 104h) [Reset = 00000000h]

RESETSSI is shown in Figure 8-67 and described in Table 8-72.

Return to the Summary Table.

RESET For SSI IPs

Figure 8-67 RESETSSI Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSSI
R-0hW-0h
Table 8-72 RESETSSI Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0SSIW0hSSI 0:
0: No action
1: Reset SSI. HW cleared.
Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.
SSI 1:
0: No action
1: Reset SSI. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.45 RESETI2S Register (Offset = 108h) [Reset = 00000000h]

RESETI2S is shown in Figure 8-68 and described in Table 8-73.

Return to the Summary Table.

RESET For I2S IP

Figure 8-68 RESETI2S Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDI2S
R-0hW-0h
Table 8-73 RESETI2S Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0I2SW0h
0: No action
1: Reset module. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.46 PDCTL0 Register (Offset = 12Ch) [Reset = 00000000h]

PDCTL0 is shown in Figure 8-69 and described in Table 8-74.

Return to the Summary Table.

Power Domain Control

Figure 8-69 PDCTL0 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPERIPH_ONSERIAL_ONRFC_ON
R-0hR/W-0hR/W-0hR/W-0h
Table 8-74 PDCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2PERIPH_ONR/W0hPERIPH Power domain.
0: PERIPH power domain is powered down
1: PERIPH power domain is powered up
1SERIAL_ONR/W0hSERIAL Power domain.
0: SERIAL power domain is powered down
1: SERIAL power domain is powered up
0RFC_ONR/W0h
0: RFC power domain powered off if also PDCTL1.RFC_ON = 0
1: RFC power domain powered on

8.8.2.47 PDCTL0RFC Register (Offset = 130h) [Reset = 00000000h]

PDCTL0RFC is shown in Figure 8-70 and described in Table 8-75.

Return to the Summary Table.

RFC Power Domain Control

Figure 8-70 PDCTL0RFC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR/W-0h
Table 8-75 PDCTL0RFC Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR/W0hAlias for PDCTL0.RFC_ON

8.8.2.48 PDCTL0SERIAL Register (Offset = 134h) [Reset = 00000000h]

PDCTL0SERIAL is shown in Figure 8-71 and described in Table 8-76.

Return to the Summary Table.

SERIAL Power Domain Control

Figure 8-71 PDCTL0SERIAL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR/W-0h
Table 8-76 PDCTL0SERIAL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR/W0hAlias for PDCTL0.SERIAL_ON

8.8.2.49 PDCTL0PERIPH Register (Offset = 138h) [Reset = 00000000h]

PDCTL0PERIPH is shown in Figure 8-72 and described in Table 8-77.

Return to the Summary Table.

PERIPH Power Domain Control

Figure 8-72 PDCTL0PERIPH Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR/W-0h
Table 8-77 PDCTL0PERIPH Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR/W0hAlias for PDCTL0.PERIPH_ON

8.8.2.50 PDSTAT0 Register (Offset = 140h) [Reset = 00000000h]

PDSTAT0 is shown in Figure 8-73 and described in Table 8-78.

Return to the Summary Table.

Power Domain Status

Figure 8-73 PDSTAT0 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPERIPH_ONSERIAL_ONRFC_ON
R-0hR-0hR-0hR-0h
Table 8-78 PDSTAT0 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2PERIPH_ONR0hPERIPH Power domain.
0: Domain may be powered down
1: Domain powered up (guaranteed)
1SERIAL_ONR0hSERIAL Power domain.
0: Domain may be powered down
1: Domain powered up (guaranteed)
0RFC_ONR0hRFC Power domain
0: Domain may be powered down
1: Domain powered up (guaranteed)

8.8.2.51 PDSTAT0RFC Register (Offset = 144h) [Reset = 00000000h]

PDSTAT0RFC is shown in Figure 8-74 and described in Table 8-79.

Return to the Summary Table.

RFC Power Domain Status

Figure 8-74 PDSTAT0RFC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR-0h
Table 8-79 PDSTAT0RFC Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR0hAlias for PDSTAT0.RFC_ON

8.8.2.52 PDSTAT0SERIAL Register (Offset = 148h) [Reset = 00000000h]

PDSTAT0SERIAL is shown in Figure 8-75 and described in Table 8-80.

Return to the Summary Table.

SERIAL Power Domain Status

Figure 8-75 PDSTAT0SERIAL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR-0h
Table 8-80 PDSTAT0SERIAL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR0hAlias for PDSTAT0.SERIAL_ON

8.8.2.53 PDSTAT0PERIPH Register (Offset = 14Ch) [Reset = 00000000h]

PDSTAT0PERIPH is shown in Figure 8-76 and described in Table 8-81.

Return to the Summary Table.

PERIPH Power Domain Status

Figure 8-76 PDSTAT0PERIPH Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR-0h
Table 8-81 PDSTAT0PERIPH Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR0hAlias for PDSTAT0.PERIPH_ON

8.8.2.54 PDCTL1 Register (Offset = 17Ch) [Reset = 0000000Ah]

PDCTL1 is shown in Figure 8-77 and described in Table 8-82.

Return to the Summary Table.

Power Domain Control

Figure 8-77 PDCTL1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDVIMS_MODERFC_ONCPU_ONRESERVED
R-0hR/W-1hR/W-0hR/W-1hR-0h
Table 8-82 PDCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-3VIMS_MODER/W1h
00: VIMS power domain is only powered when CPU power domain is powered.
01: VIMS power domain is powered whenever the BUS power domain is powered.
1X: Block power up of VIMS power domain at next wake up. This mode only has effect when VIMS power domain is not powered. Used for Autonomous RF Core.
2RFC_ONR/W0h 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power domain powered on Bit shall be used by RFC in autonomous mode but there is no HW restrictions fom system CPU to access the bit.
1CPU_ONR/W1h
0: Causes a power down of the CPU power domain when system CPU indicates it is idle.
1: Initiates power-on of the CPU power domain.
This bit is automatically set by a WIC power-on event.
0RESERVEDR0hReserved

8.8.2.55 PDCTL1CPU Register (Offset = 184h) [Reset = 00000001h]

PDCTL1CPU is shown in Figure 8-78 and described in Table 8-83.

Return to the Summary Table.

CPU Power Domain Direct Control

Figure 8-78 PDCTL1CPU Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR/W-1h
Table 8-83 PDCTL1CPU Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR/W1hThis is an alias for PDCTL1.CPU_ON

8.8.2.56 PDCTL1RFC Register (Offset = 188h) [Reset = 00000000h]

PDCTL1RFC is shown in Figure 8-79 and described in Table 8-84.

Return to the Summary Table.

RFC Power Domain Direct Control

Figure 8-79 PDCTL1RFC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR/W-0h
Table 8-84 PDCTL1RFC Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR/W0hThis is an alias for PDCTL1.RFC_ON

8.8.2.57 PDCTL1VIMS Register (Offset = 18Ch) [Reset = 00000001h]

PDCTL1VIMS is shown in Figure 8-80 and described in Table 8-85.

Return to the Summary Table.

VIMS Mode Direct Control

Figure 8-80 PDCTL1VIMS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDMODE
R-0hR/W-1h
Table 8-85 PDCTL1VIMS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0MODER/W1hThis is an alias for PDCTL1.VIMS_MODE

8.8.2.58 PDSTAT1 Register (Offset = 194h) [Reset = 0000001Ah]

PDSTAT1 is shown in Figure 8-81 and described in Table 8-86.

Return to the Summary Table.

Power Manager Status

Figure 8-81 PDSTAT1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDBUS_ONVIMS_ONRFC_ONCPU_ONRESERVED
R-0hR-1hR-1hR-0hR-1hR-0h
Table 8-86 PDSTAT1 Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4BUS_ONR1h
0: BUS domain not accessible
1: BUS domain is currently accessible
3VIMS_ONR1h
0: VIMS domain not accessible
1: VIMS domain is currently accessible
2RFC_ONR0h
0: RFC domain not accessible
1: RFC domain is currently accessible
1CPU_ONR1h
0: CPU and BUS domain not accessible
1: CPU and BUS domains are both currently accessible
0RESERVEDR0hReserved

8.8.2.59 PDSTAT1BUS Register (Offset = 198h) [Reset = 00000001h]

PDSTAT1BUS is shown in Figure 8-82 and described in Table 8-87.

Return to the Summary Table.

BUS Power Domain Direct Read Status

Figure 8-82 PDSTAT1BUS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR-1h
Table 8-87 PDSTAT1BUS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR1hThis is an alias for PDSTAT1.BUS_ON

8.8.2.60 PDSTAT1RFC Register (Offset = 19Ch) [Reset = 00000000h]

PDSTAT1RFC is shown in Figure 8-83 and described in Table 8-88.

Return to the Summary Table.

RFC Power Domain Direct Read Status

Figure 8-83 PDSTAT1RFC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR-0h
Table 8-88 PDSTAT1RFC Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR0hThis is an alias for PDSTAT1.RFC_ON

8.8.2.61 PDSTAT1CPU Register (Offset = 1A0h) [Reset = 00000001h]

PDSTAT1CPU is shown in Figure 8-84 and described in Table 8-89.

Return to the Summary Table.

CPU Power Domain Direct Read Status

Figure 8-84 PDSTAT1CPU Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR-1h
Table 8-89 PDSTAT1CPU Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR1hThis is an alias for PDSTAT1.CPU_ON

8.8.2.62 PDSTAT1VIMS Register (Offset = 1A4h) [Reset = 00000001h]

PDSTAT1VIMS is shown in Figure 8-85 and described in Table 8-90.

Return to the Summary Table.

VIMS Mode Direct Read Status

Figure 8-85 PDSTAT1VIMS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDON
R-0hR-1h
Table 8-90 PDSTAT1VIMS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ONR1hThis is an alias for PDSTAT1.VIMS_ON

8.8.2.63 RFCBITS Register (Offset = 1CCh) [Reset = 00000000h]

RFCBITS is shown in Figure 8-86 and described in Table 8-91.

Return to the Summary Table.

Control To RFC

Figure 8-86 RFCBITS Register
313029282726252423222120191817161514131211109876543210
READ
R/W-0h
Table 8-91 RFCBITS Register Field Descriptions
BitFieldTypeResetDescription
31-0READR/W0hControl bits for RFC. The RF core CPE processor will automatically check this register when it boots, and it can be used to immediately instruct CPE to perform some tasks at its start-up. The supported functionality is ROM-defined and may vary. See the technical reference manual for more details.

8.8.2.64 RFCMODESEL Register (Offset = 1D0h) [Reset = 00000000h]

RFCMODESEL is shown in Figure 8-87 and described in Table 8-92.

Return to the Summary Table.

Selected RFC Mode

Figure 8-87 RFCMODESEL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCURR
R-0hR/W-0h
Table 8-92 RFCMODESEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CURRR/W0hSelects the set of commands that the RFC will accept. Only modes permitted by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for details.
0h = Select Mode 0
1h = Select Mode 1
2h = Select Mode 2
3h = Select Mode 3
4h = Select Mode 4
5h = Select Mode 5
6h = Select Mode 6
7h = Select Mode 7

8.8.2.65 RFCMODEHWOPT Register (Offset = 1D4h) [Reset = 00000000h]

RFCMODEHWOPT is shown in Figure 8-88 and described in Table 8-93.

Return to the Summary Table.

Allowed RFC Modes

Figure 8-88 RFCMODEHWOPT Register
313029282726252423222120191817161514131211109876543210
RESERVEDAVAIL
R-0hR-0h
Table 8-93 RFCMODEHWOPT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0AVAILR0hPermitted RFC modes. More than one mode can be permitted.
1h = Mode 0 permitted
2h = Mode 1 permitted
4h = Mode 2 permitted
8h = Mode 3 permitted
10h = Mode 4 permitted
20h = Mode 5 permitted
40h = Mode 6 permitted
80h = Mode 7 permitted

8.8.2.66 PWRPROFSTAT Register (Offset = 1E0h) [Reset = 00000001h]

PWRPROFSTAT is shown in Figure 8-89 and described in Table 8-94.

Return to the Summary Table.

Power Profiler Register

Figure 8-89 PWRPROFSTAT Register
313029282726252423222120191817161514131211109876543210
RESERVEDVALUE
R-0hR/W-1h
Table 8-94 PWRPROFSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0VALUER/W1hSW can use these bits to timestamp the application. These bits are also available through the testtap and can thus be used by the emulator to profile in real time.

8.8.2.67 MCUSRAMCFG Register (Offset = 21Ch) [Reset = 00000020h]

MCUSRAMCFG is shown in Figure 8-90 and described in Table 8-95.

Return to the Summary Table.

MCU SRAM configuration

Figure 8-90 MCUSRAMCFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDBM_OFFPAGEPGSBMPCH_FPCH_L
R-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-95 MCUSRAMCFG Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5BM_OFFR/W1hBurst Mode disable
0: Burst Mode enabled.
1: Burst Mode off.
4PAGER/W0hPage Mode select
0: Page Mode disabled. Memory works in standard mode
1: Page Mode enabled. Only one half of butterfly array selected. Page Mode will select either LSB half or MSB half of the word based on PGS setting.
This mode can be used for additional power saving
3PGSR/W0h0: Select LSB half of word during Page Mode, PAGE = 1
1: Select MSB half of word during Page Mode, PAGE = 1
2BMR/W0hBurst Mode Enable
0: Burst Mode Disable. Memory works in standard mode.
1: Burst Mode Enable
When in Burst Mode bitline precharge and wordline firing depends on PCH_F and PCH_L.
Burst Mode results in reduction in active power.
1PCH_FR/W0h0: No bitline precharge in second half of cycle
1: Bitline precharge in second half of cycle when in Burst Mode, BM = 1
0PCH_LR/W0h0: No bitline precharge in first half of cycle
1: Bitline precharge in first half of cycle when in Burst Mode, BM = 1

8.8.2.68 RAMRETEN Register (Offset = 224h) [Reset = 0000000Bh]

RAMRETEN is shown in Figure 8-91 and described in Table 8-96.

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Memory Retention Control

Figure 8-91 RAMRETEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRFCULLRFCVIMS
R-0hR/W-1hR/W-0hR/W-3h
Table 8-96 RAMRETEN Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3RFCULLR/W1h0: Retention for RFC ULL SRAM disabled
1: Retention for RFC ULL SRAM enabled
Memories controlled:
CPEULLRAM
2RFCR/W0h0: Retention for RFC SRAM disabled
1: Retention for RFC SRAM enabled
Memories controlled: CPERAM MCERAM RFERAM DSBRAM
1-0VIMSR/W3h
0: Memory retention disabled
1: Memory retention enabled
Bit 0: VIMS_TRAM
Bit 1: VIMS_CRAM
Legal modes depend on settings in VIMS:CTL.MODE
00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to CACHE or SPLIT mode after waking up again
01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in GPRAM mode after wake up, alternatively select OFF mode first and then CACHE or SPILT mode.
10: Illegal mode
11: No restrictions

8.8.2.69 OSCIMSC Register (Offset = 290h) [Reset = 00000036h]

OSCIMSC is shown in Figure 8-92 and described in Table 8-97.

Return to the Summary Table.

Oscillator Interrupt Mask Control

Figure 8-92 OSCIMSC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
HFSRCPENDIMLFSRCDONEIMXOSCDLFIMXOSCLFIMRCOSCDLFIMRCOSCLFIMXOSCHFIMRCOSCHFIM
R/W-0hR/W-0hR/W-1hR/W-1hR/W-0hR/W-1hR/W-1hR/W-0h
Table 8-97 OSCIMSC Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7HFSRCPENDIMR/W0h0: Disable interrupt generation when HFSRCPEND is qualified
1: Enable interrupt generation when HFSRCPEND is qualified
6LFSRCDONEIMR/W0h0: Disable interrupt generation when LFSRCDONE is qualified
1: Enable interrupt generation when LFSRCDONE is qualified
5XOSCDLFIMR/W1h0: Disable interrupt generation when XOSCDLF is qualified
1: Enable interrupt generation when XOSCDLF is qualified
4XOSCLFIMR/W1h0: Disable interrupt generation when XOSCLF is qualified
1: Enable interrupt generation when XOSCLF is qualified
3RCOSCDLFIMR/W0h0: Disable interrupt generation when RCOSCDLF is qualified
1: Enable interrupt generation when RCOSCDLF is qualified
2RCOSCLFIMR/W1h0: Disable interrupt generation when RCOSCLF is qualified
1: Enable interrupt generation when RCOSCLF is qualified
1XOSCHFIMR/W1h0: Disable interrupt generation when XOSCHF is qualified
1: Enable interrupt generation when XOSCHF is qualified
0RCOSCHFIMR/W0h0: Disable interrupt generation when RCOSCHF is qualified
1: Enable interrupt generation when RCOSCHF is qualified

8.8.2.70 OSCRIS Register (Offset = 294h) [Reset = 00000000h]

OSCRIS is shown in Figure 8-93 and described in Table 8-98.

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Oscillator Raw Interrupt Status

Figure 8-93 OSCRIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
HFSRCPENDRISLFSRCDONERISXOSCDLFRISXOSCLFRISRCOSCDLFRISRCOSCLFRISXOSCHFRISRCOSCHFRIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-98 OSCRIS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7HFSRCPENDRISR0hSCLK_HF source switch pending interrupt.
After a write to DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL leads to a SCLK_HF source change request, then the requested SCLK_HF source will be enabled and qualified. When the new source is ready to be used as a clock source, then the interrupt HSSRCPENDRIS will go high. When the Flash allows SCLK_HF source switching to take place after flash memory read access is disabled. At this time the actual SCLK_HF clock source switch will be performed, and the interrupt status HSSRCPENDRIS will go low.
0: Indicates SCLK_HF source is not ready to be switched
1: Indicates SCLK_HF source is ready to be switched
Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.
Set by HW. Cleared by writing to OSCICR.HFSRCPENDC
6LFSRCDONERISR0hSCLK_LF source switch done.
The DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL register field is used to request that the SCLK_LF source shall be changed. After an SCLK_LF clock source change is requested, the new source may need to be enabled and qualified before switching of clock source can be done. The interrupt LFRSRCDONERIS goes high to indicate that the SCLK_LF clock source switching has been performed. LFRSRCDONERIS will go low again when the next clock source change is requested by writing to DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL .
0: Indicates SCLK_LF source switch has not completed
1: Indicates SCLK_LF source switch has completed
Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.
Set by HW. Cleared by writing to OSCICR.LFSRCDONEC
5XOSCDLFRISR0hThe XOSCDLFRIS interrupt indicates when the XOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF. When XOSCDLFRIS is high, XOSC_HF will be used as source for SCLK_LF when selected. When none of the system clocks have XOSC_HF selected as clock source, the XOSC_HF source is automatically disabled and the XOSCDLFRIS interrupt status will go low.
0: XOSCDLF has not been qualified
1: XOSCDLF has been qualified
Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.
Set by HW. Cleared by writing to OSCICR.XOSCDLFC
4XOSCLFRISR0hThe XOSCLFRIS interrupt indicates when the output of the XOSC_LF oscillator has been qualified with respect to frequency. The XOSCLFRIS interrupt status goes high when the XOSC_LF oscillator is ready to be used as a clock source.
After the clock qualification is successful, XOSCLFRIS interrupt status remains high, and further qualification is turned off until the XOSC_LF oscillator is disabled. XOSCLFRIS interrupt status will go low only at initial power-on, or after the XOSC_LF oscillator has been disabled when being deselected as a clock source.
0: XOSCLF has not been qualified
1: XOSCLF has been qualified
Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.
Set by HW. Cleared by writing to OSCICR.XOSCLFC
3RCOSCDLFRISR0hThe RCOSCDLFRIS interrupt indicates when the RCOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF. When RCOSCDLFRIS is high, RCOSC_HF will be used as source for SCLK_LF when selected. When none of the system clocks have RCOSC_HF selected as clock source, the RCOSC_HF source is automatically disabled and the RCOSCDLFRIS interrupt status will go low.
If the SCLK_LF or ACLK_REF source is changed from RCOSC_HF derived to XOSC_HF derived low-frequency clock and the new source has not been qualified, then the clock will remain running on the original source. The RCOSCDLFRIS interrupt will then remain high.
0: RCOSCDLF has not been qualified
1: RCOSCDLF has been qualified
Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.
Set by HW. Cleared by writing to OSCICR.RCOSCDLFC
2RCOSCLFRISR0hThe RCOSCLFRIS interrupt indicates when the output of the RCOSC_LF oscillator has been qualified with respect to frequency. The RCOSCLFRIS interrupt status goes high when the RCOSC_LF oscillator is ready to be used as a clock source.
After the clock qualification is successful, RCOSCLFRIS interrupt status remains high, and further qualification is turned off until the RCOSC_LF oscillator is disabled. RCOSCLFRIS interrupt status will go low only at initial power-on, or after the RCOSC_LF oscillator has been disabled when being deselected as a clock source.
0: RCOSCLF has not been qualified
1: RCOSCLF has been qualified
Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.
Set by HW. Cleared by writing to OSCICR.RCOSCLFC
1XOSCHFRISR0hThe XOSCHFRIS interrupt indicates when the XOSC_HF oscillator has been qualified for use as a clock source. XOSCHFRIS is also used in TCXO mode (when DDI_0_OSC:XOSCHFCTL.TCXO_MODE is 1).
When the XOSCHFRIS interrupt is high, the oscillator is qualified and will be used as a clock source when selected. The XOSCHFRIS interrupt goes low when the oscillator is disabled after being deselected as a clock source.
0: XOSC_HF has not been qualified
1: XOSC_HF has been qualified
Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.
Set by HW. Cleared by writing to OSCICR.XOSCHFC
0RCOSCHFRISR0hThe RCOSCHFRIS interrupt indicates when the RCOSC_HF oscillator has been qualified for use as a clock source When the RCOSCHFRIS interrupt is high, the oscillator is qualified and will be used as a clock source when selected. The RCOSCHFRIS interrupt goes low when the oscillator is disabled after being deselected as a clock source.
0: RCOSC_HF has not been qualified
1: RCOSC_HF has been qualified
Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.
Set by HW. Cleared by writing to OSCICR.RCOSCHFC

8.8.2.71 OSCICR Register (Offset = 298h) [Reset = 00000000h]

OSCICR is shown in Figure 8-94 and described in Table 8-99.

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Oscillator Raw Interrupt Clear

Figure 8-94 OSCICR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
HFSRCPENDCLFSRCDONECXOSCDLFCXOSCLFCRCOSCDLFCRCOSCLFCXOSCHFCRCOSCHFC
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 8-99 OSCICR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7HFSRCPENDCW0hWriting 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 has no effect.
6LFSRCDONECW0hWriting 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 has no effect.
5XOSCDLFCW0hWriting 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 has no effect.
4XOSCLFCW0hWriting 1 to this field clears the XOSCLF raw interrupt status. Writing 0 has no effect.
3RCOSCDLFCW0hWriting 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 has no effect.
2RCOSCLFCW0hWriting 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 has no effect.
1XOSCHFCW0hWriting 1 to this field clears the XOSCHF raw interrupt status. Writing 0 has no effect.
0RCOSCHFCW0hWriting 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 has no effect.