SWCU185G January 2018 – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
The WCLK and ADx signals are updated on one edge of the BCLK and sampled on the opposite edge.
The sample words transferred on the ADx pins are aligned with the WCLK signal, according to the configured serial interface format. The first WCLK edge of a sample word is either rising or falling, depending on the configured serial interface format.
The period from the first WCLK edge of an audio sample (one or more channels) to the first WCLK edge of the next audio sample is called a frame. A frame consists of either one or two phases. A phase is divided into the following intervals:
A sample word on the serial interface can contain from 8 to 24 bits.