SWCU185G January 2018 – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
Table 13-9 shows the AES Initialization Vector registers that are used to provide and read the IV from the AES engine.
AES_IV_0, (Read/Write), 32-bit Address Offset: 0x540 AES_IV_1, (Read/Write), 32-bit Address Offset: 0x544 AES_IV_2, (Read/Write), 32-bit Address Offset: 0x548 AES_IV_3, (Read/Write), 32-bit Address Offset: 0x54C |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AES_IV[31:0] AES_IV[63:32] AES_IV[95:64] AES_IV[127:96] | |||||||||||||||||||||||||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits | Name | Description |
---|---|---|
127–0 | AES_IV | For regular AES operations (CBC and CTR), these registers must be written with a new 128-bit IV.
After an operation, these registers contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode is selected, this value is incremented with 0x1 (after first use) when a new data block is submitted to the engine. |
Bits | Name | Description |
---|---|---|
127–0 | AES_IV | For GCM operations, these registers must be written with a new 128-bit IV. After an operation, these registers contain the updated 128-bit result IV, generated by the EIP-120t. Bits [127–96] of the IV represent the initial counter value (which is 1 for GCM) and must therefore be initialized to 0x0100 0000. This value is incremented with 0x1 (after first use) when a new data block is submitted to the engine. |
Bits | Name | Description |
---|---|---|
127–0 | A0 | For CCM, this field must be written with value A0. This value is the concatenation of:
A0-flags (5 bits of zero and 3 bits L), nonce and counter value. L must be a copy from the L value of the AESCTL register. This L indicates the width of the nonce and counter. The loaded counter must be initialized to zero. The total width of A0 is 128 bits. |
Bit | Name | Description |
---|---|---|
127–0 | Zeroes | For CBC-MAC this register must be written with zeroes at the start of each operation. After an operation, these registers contain the 128-bit TAG output, generated by the crypto core. |