SWCU185G January 2018 – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
Table 20-16 describes the AUX_PROG_DLY_IDLE event. The level of this event depends on the value of the 16-bit AUX_EVCTL:PROGDLY counter. When the counter value is zero, the level is high; otherwise, the level is low.
When the counter is loaded with a nonzero value, it decrements by 1 LSB for each edge of a 500 kHz clock with 50% duty cycle until the counter value is zero. The 500 kHz clock signal is synchronized at the SCE rate. Hence, one LSB corresponds to a 1 µs delay on average because the edge-detect logic is susceptible to synchronization jitter.
The next example shows how to delay further Sensor Controller execution by a minimum of 15 µs.
# Sample assembly (Example code produced by the Sensor Controller Studio)
0: ld R4, #(15+1) ; Load value for AUX_EVCTL:PROGDLY counter
1: out R4, [#IOP_EVCTL_PROGDLY] ; Load the AUX_EVCTL:PROGDLY counter
2: wev1 #0 ; Wait until AUX_EVCTL:PROGDLY counter is 0.
3: ...
# The Sensor Controller uses the alias I/O memory space
IOP_EVCTL_PROGDLY equ 73
The AUX_EVCTL:PROGDLY write instant and the 500 kHz clock edges have random phase. Therefore, it is required to add 1 µs to the 15 µs to ensure a delay of at least 15 µs.
The AUX_EVCTL:PROGDLY counter is functional only in Active and Low-Power operational modes. The AUX_PROG_DLY_IDLE event must not be used in power-down operational mode.