SWCU185G January 2018 – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
The prescaler optionally divides the Timer2 clock. The divided clock determines the:
AUX_TIMER2:PRECFG.CLKDIV sets the division. Division ranges from 1 to 256. Registers are accessed at the Timer2 clock.