SWCU185G January 2018 – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
The AON IOC contains the output enable control for the 32 kHz LF system clock output, and the clock signal has its own PORTID called AON_CLK32K (0x7). This makes it easy to output the clock signal to a pin. Map the clock to a chosen DIO, and enable the clock output by setting the AON_IOC:CLK32KCTL.OE_N register field to 0x0. The following two driver library calls achieve the same result:
#include <driverlib/aon_ioc.h>
IOCPortConfigureSet(IOIDn, IOC_PORT_AON_CLK32K, IOC_STD_OUTPUT);
AONIOC32kHzOutputEnable();
This outputs the LF system clock signal in all power modes except for shutdown.
The AON_CLK32K PORTID value is also chosen when using a DIO as the input source for the 32 kHz LF system clock. For a description of how to use a DIO as the clock source, see Chapter 8.
The AON_CLK32K PORTID must be used as only a single clock output or as only a clock input.