SWCU191 February   2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA

 

  1. 1 Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  2. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Analog Peripherals
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  3. 3 Arm® Cortex®-M4 Processor
    1. 3.1 Arm® Cortex®-M4 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Arm® Cortex®-M4 System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4 Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4 Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Arm® Cortex®-M4 Processor Registers
      1. 3.7.1 CPU_DWT Registers
      2. 3.7.2 CPU_FPB Registers
      3. 3.7.3 CPU_ITM Registers
      4. 3.7.4 CPU_SCS Registers
      5. 3.7.5 CPU_TPIU Registers
  4. 4 Memory Map
    1. 4.1 Memory Map
  5. 5 Arm® Cortex®-M4 Peripherals
    1. 5.1 Arm® Cortex®-M4 Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  6. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  7. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  8. 8 Power, Reset and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 OSC_DIG Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  9. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  10. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM Registers
  11. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  13. 13Cryptography
    1. 13.1 AES Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master Transfer Protection
          1. 13.5.4.2.1 Master Transfer Protection Control
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Encryption and Decryption
        1. 13.7.3.1 Key Store
          1. 13.7.3.1.1 Load Keys From External Memory
        2. 13.7.3.2 Basic AES Modes
          1. 13.7.3.2.1 AES-ECB
          2. 13.7.3.2.2 AES-CBC
          3. 13.7.3.2.3 AES-CTR
          4. 13.7.3.2.4 Programming Sequence With DMA Data
        3. 13.7.3.3 CBC-MAC
          1. 13.7.3.3.1 Programming Sequence for CBC-MAC
        4. 13.7.3.4 AES-CCM
          1. 13.7.3.4.1 Programming Sequence for AES-CCM
      4. 13.7.4 Exceptions Handling
        1. 13.7.4.1 Soft Reset
        2. 13.7.4.2 External Port Errors
        3. 13.7.4.3 Key Store Errors
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  14. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  15. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 μDMA Registers
  16. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  17. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  18. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  19. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  20. 20AUX Domain Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
      3. 20.2.3 SCE Clock Emulation
    3. 20.3 Digital Peripheral Modules
      1. 20.3.1 Overview
        1. 20.3.1.1 DDI Control-Configuration
      2. 20.3.2 AIODIO
        1. 20.3.2.1 Introduction
        2. 20.3.2.2 Functional Description
          1. 20.3.2.2.1 Mapping to DIO Pins
          2. 20.3.2.2.2 Configuration
          3. 20.3.2.2.3 GPIO Mode
          4. 20.3.2.2.4 Input Buffer
          5. 20.3.2.2.5 Data Output Source
      3. 20.3.3 SMPH
        1. 20.3.3.1 Introduction
        2. 20.3.3.2 Functional Description
        3. 20.3.3.3 Semaphore Allocation in TI Software
      4. 20.3.4 Time-to-Digital Converter (TDC)
        1. 20.3.4.1 Introduction
        2. 20.3.4.2 Functional Description
          1. 20.3.4.2.1 Command
          2. 20.3.4.2.2 Conversion Time Configuration
          3. 20.3.4.2.3 Status and Result
          4. 20.3.4.2.4 Clock Source Selection
            1. 20.3.4.2.4.1 Counter Clock
            2. 20.3.4.2.4.2 Reference Clock
          5. 20.3.4.2.5 Start and Stop Events
          6. 20.3.4.2.6 Prescaler
        3. 20.3.4.3 Supported Measurement Types
          1. 20.3.4.3.1 Measure Pulse Width
          2. 20.3.4.3.2 Measure Frequency
          3. 20.3.4.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.3.4.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.3.4.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.3.4.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.3.4.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.3.4.3.4 Pulse Counting
      5. 20.3.5 Timer01
        1. 20.3.5.1 Introduction
        2. 20.3.5.2 Functional Description
    4. 20.4 Analog Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 ADI Control-Configuration
        2. 20.4.1.2 Block Diagram
      2. 20.4.2 Analog-to-Digital Converter (ADC)
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Input Selection and Scaling
          2. 20.4.2.2.2 Reference Selection
          3. 20.4.2.2.3 ADC Sample Mode
          4. 20.4.2.2.4 ADC Clock Source
          5. 20.4.2.2.5 ADC Trigger
          6. 20.4.2.2.6 Sample FIFO
          7. 20.4.2.2.7 µDMA Interface
          8. 20.4.2.2.8 Resource Ownership and Usage
      3. 20.4.3 COMPA
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
          1. 20.4.3.2.1 Input Selection
          2. 20.4.3.2.2 Reference Selection
          3. 20.4.3.2.3 LPM Bias and COMPA Enable
          4. 20.4.3.2.4 Resource Ownership and Usage
      4. 20.4.4 COMPB
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 Input Selection
          2. 20.4.4.2.2 Reference Selection
          3. 20.4.4.2.3 Resource Ownership and Usage
            1. 20.4.4.2.3.1 System CPU Wakeup
      5. 20.4.5 Reference DAC
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Reference Selection
          2. 20.4.5.2.2 Output Voltage Control and Range
          3. 20.4.5.2.3 Sample Clock
            1. 20.4.5.2.3.1 Automatic Phase Control
            2. 20.4.5.2.3.2 Manual Phase Control
            3. 20.4.5.2.3.3 Operational Mode Dependency
          4. 20.4.5.2.4 Output Selection
            1. 20.4.5.2.4.1 Buffer
            2. 20.4.5.2.4.2 External Load
            3. 20.4.5.2.4.3 COMPA_REF
            4. 20.4.5.2.4.4 COMPB_REF
          5. 20.4.5.2.5 LPM Bias
          6. 20.4.5.2.6 Resource Ownership and Usage
      6. 20.4.6 ISRC
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
          1. 20.4.6.2.1 Programmable Current
          2. 20.4.6.2.2 Voltage Reference
          3. 20.4.6.2.3 ISRC Enable
          4. 20.4.6.2.4 Temperature Dependency
          5. 20.4.6.2.5 Resource Ownership and Usage
    5. 20.5 Event Routing and Usage
      1. 20.5.1 AUX Event Bus
        1. 20.5.1.1 Event Signals
        2. 20.5.1.2 Event Subscribers
          1. 20.5.1.2.1 Event Detection
            1. 20.5.1.2.1.1 Detection of Asynchronous Events
            2. 20.5.1.2.1.2 Detection of Synchronous Events
      2. 20.5.2 Event Observation on External Pin
      3. 20.5.3 Events From MCU Domain
      4. 20.5.4 Events to MCU Domain
      5. 20.5.5 Events From AON Domain
      6. 20.5.6 Events to AON Domain
      7. 20.5.7 µDMA Interface
    6. 20.6 AUX Domain Peripheral Registers
      1. 20.6.1 ADI_4_AUX Registers
      2. 20.6.2 AUX_AIODIO Registers
      3. 20.6.3 AUX_EVCTL Registers
      4. 20.6.4 AUX_SMPH Registers
      5. 20.6.5 AUX_TDC Registers
      6. 20.6.6 AUX_TIMER01 Registers
      7. 20.6.7 AUX_ANAIF Registers
      8. 20.6.8 AUX_SYSIF Registers
  21. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  22. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  23. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  24. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  25. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  26. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
        1.       Revision History

3.7.4 CPU_SCS Registers

Table 3-101 lists the memory-mapped registers for the CPU_SCS registers. All register offset addresses not listed in Table 3-101 should be considered as reserved locations and the register contents should not be modified.

Table 3-101 CPU_SCS Registers
OffsetAcronymRegister NameSection
4hICTRInterrupt Control Type#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ICTR
8hACTLRAuxiliary Control#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ACTLR
10hSTCSRSysTick Control and Status#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STCSR
14hSTRVRSysTick Reload Value#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STRVR
18hSTCVRSysTick Current Value#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STCVR
1ChSTCRSysTick Calibration Value#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STCR
100hNVIC_ISER0Irq 0 to 31 Set Enable#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISER0
104hNVIC_ISER1Irq 32 to 63 Set Enable#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISER1
180hNVIC_ICER0Irq 0 to 31 Clear Enable#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICER0
184hNVIC_ICER1Irq 32 to 63 Clear Enable#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICER1
200hNVIC_ISPR0Irq 0 to 31 Set Pending#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISPR0
204hNVIC_ISPR1Irq 32 to 63 Set Pending#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISPR1
280hNVIC_ICPR0Irq 0 to 31 Clear Pending#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICPR0
284hNVIC_ICPR1Irq 32 to 63 Clear Pending#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICPR1
300hNVIC_IABR0Irq 0 to 31 Active Bit#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IABR0
304hNVIC_IABR1Irq 32 to 63 Active Bit#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IABR1
400hNVIC_IPR0Irq 0 to 3 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR0
404hNVIC_IPR1Irq 4 to 7 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR1
408hNVIC_IPR2Irq 8 to 11 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR2
40ChNVIC_IPR3Irq 12 to 15 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR3
410hNVIC_IPR4Irq 16 to 19 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR4
414hNVIC_IPR5Irq 20 to 23 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR5
418hNVIC_IPR6Irq 24 to 27 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR6
41ChNVIC_IPR7Irq 28 to 31 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR7
420hNVIC_IPR8Irq 32 to 35 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR8
424hNVIC_IPR9Irq 32 to 35 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR9
D00hCPUIDCPUID Base#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CPUID
D04hICSRInterrupt Control State#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ICSR
D08hVTORVector Table Offset#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_VTOR
D0ChAIRCRApplication Interrupt/Reset Control#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_AIRCR
D10hSCRSystem Control#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SCR
D14hCCRConfiguration Control#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CCR
D18hSHPR1System Handlers 4-7 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHPR1
D1ChSHPR2System Handlers 8-11 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHPR2
D20hSHPR3System Handlers 12-15 Priority#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHPR3
D24hSHCSRSystem Handler Control and State#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHCSR
D28hCFSRConfigurable Fault Status#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CFSR
D2ChHFSRHard Fault Status#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_HFSR
D30hDFSRDebug Fault Status#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DFSR
D34hMMFARMem Manage Fault Address#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MMFAR
D38hBFARBus Fault Address#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_BFAR
D3ChAFSRAuxiliary Fault Status#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_AFSR
D40hID_PFR0Processor Feature 0#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_PFR0
D44hID_PFR1Processor Feature 1#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_PFR1
D48hID_DFR0Debug Feature 0#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_DFR0
D4ChID_AFR0Auxiliary Feature 0#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_AFR0
D50hID_MMFR0Memory Model Feature 0#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR0
D54hID_MMFR1Memory Model Feature 1#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR1
D58hID_MMFR2Memory Model Feature 2#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR2
D5ChID_MMFR3Memory Model Feature 3#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR3
D60hID_ISAR0ISA Feature 0#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR0
D64hID_ISAR1ISA Feature 1#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR1
D68hID_ISAR2ISA Feature 2#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR2
D6ChID_ISAR3ISA Feature 3#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR3
D70hID_ISAR4ISA Feature 4#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR4
D88hCPACRCoprocessor Access Control#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CPACR
D90hMPU_TYPEMPU Type#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_TYPE
D94hMPU_CTRLMPU Control#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_CTRL
D98hMPU_RNRMPU Region Number#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RNR
D9ChMPU_RBARMPU Region Base Address#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR
DA0hMPU_RASRMPU Region Attribute and Size#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR
DA4hMPU_RBAR_A1MPU Alias 1 Region Base Address#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_A1
DA8hMPU_RASR_A1MPU Alias 1 Region Attribute and Size#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_A1
DAChMPU_RBAR_A2MPU Alias 2 Region Base Address#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_A2
DB0hMPU_RASR_A2MPU Alias 2 Region Attribute and Size#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_A2
DB4hMPU_RBAR_A3MPU Alias 3 Region Base Address#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_A3
DB8hMPU_RASR_A3MPU Alias 3 Region Attribute and Size#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_A3
DF0hDHCSRDebug Halting Control and Status#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DHCSR
DF4hDCRSRDeubg Core Register Selector#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DCRSR
DF8hDCRDRDebug Core Register Data#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DCRDR
DFChDEMCRDebug Exception and Monitor Control#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DEMCR
F00hSTIRSoftware Trigger Interrupt#CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STIR

Complex bit access types are encoded to fit into small table cells. Table 3-102 shows the codes that are used for access types in this section.

Table 3-102 CPU_SCS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

3.7.4.1 ICTR Register (Offset = 4h) [Reset = 00000001h]

ICTR is shown in Figure 3-71 and described in Table 3-103.

Return to the Summary Table.

Interrupt Control Type
Read this register to see the number of interrupt lines that the NVIC supports.

Figure 3-71 ICTR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINTLINESNUM
R-0hR-1h
Table 3-103 ICTR Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2-0INTLINESNUMR1hTotal number of interrupt lines in groups of 32.
0: 0...32
1: 33...64
2: 65...96
3: 97...128
4: 129...160
5: 161...192
6: 193...224
7: 225...256

3.7.4.2 ACTLR Register (Offset = 8h) [Reset = 00000000h]

ACTLR is shown in Figure 3-72 and described in Table 3-104.

Return to the Summary Table.

Auxiliary Control
This register is used to disable certain aspects of functionality within the processor

Figure 3-72 ACTLR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDRESERVEDDISFPCA
R/W-0hR/W-0hR/W-0h
76543210
RESERVEDDISFOLDDISDEFWBUFDISMCYCINT
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-104 ACTLR Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8DISFPCAR/W0hDisable automatic update of CONTROL.FPCA
7-3RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2DISFOLDR/W0hDisables folding of IT instruction.
1DISDEFWBUFR/W0hDisables write buffer use during default memory map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed.
0DISMCYCINTR/W0hDisables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs.

3.7.4.3 STCSR Register (Offset = 10h) [Reset = 00000004h]

STCSR is shown in Figure 3-73 and described in Table 3-105.

Return to the Summary Table.

SysTick Control and Status
This register enables the SysTick features and returns status flags related to SysTick.

Figure 3-73 STCSR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCOUNTFLAG
R-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLKSOURCETICKINTENABLE
R-0hR-1hR/W-0hR/W-0h
Table 3-105 STCSR Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
16COUNTFLAGR0hReturns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the **AHB-AP** Control Register is set to 0. Otherwise, COUNTFLAG is not changed by the debugger read.
15-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2CLKSOURCER1hClock source:
0: External reference clock.
1: Core clock
External clock is not available in this device. Writes to this field will be ignored.
1TICKINTR/W0h0: Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero.
1: Counting down to zero pends the SysTick handler.
0ENABLER/W0hEnable SysTick counter
0: Counter disabled
1: Counter operates in a multi-shot way. That is, counter loads with the Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads STRVR.RELOAD again, and begins counting.

3.7.4.4 STRVR Register (Offset = 14h) [Reset = 00000000h]

STRVR is shown in Figure 3-74 and described in Table 3-106.

Return to the Summary Table.

SysTick Reload Value
This register is used to specify the start value to load into the current value register STCVR.CURRENT when the counter reaches 0. It can be any value between 1 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and STCSR.COUNTFLAG are activated when counting from 1 to 0.

Figure 3-74 STRVR Register
313029282726252423222120191817161514131211109876543210
RESERVEDRELOAD
R/W-0hR/W-X
Table 3-106 STRVR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
23-0RELOADR/WXValue to load into the SysTick Current Value Register STCVR.CURRENT when the counter reaches 0.

3.7.4.5 STCVR Register (Offset = 18h) [Reset = 00000000h]

STCVR is shown in Figure 3-75 and described in Table 3-107.

Return to the Summary Table.

SysTick Current Value
Read from this register returns the current value of SysTick counter. Writing to this register resets the SysTick counter (as well as STCSR.COUNTFLAG).

Figure 3-75 STCVR Register
313029282726252423222120191817161514131211109876543210
RESERVEDCURRENT
R/W-0hR/W-X
Table 3-107 STCVR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
23-0CURRENTR/WXCurrent value at the time the register is accessed. No read-modify-write protection is provided, so change with care. Writing to it with any value clears the register to 0. Clearing this register also clears STCSR.COUNTFLAG.

3.7.4.6 STCR Register (Offset = 1Ch) [Reset = C0075300h]

STCR is shown in Figure 3-76 and described in Table 3-108.

Return to the Summary Table.

SysTick Calibration Value
Used to enable software to scale to any required speed using divide and multiply.

Figure 3-76 STCR Register
3130292827262524
NOREFSKEWRESERVED
R-1hR-1hR-0h
2322212019181716
TENMS
R-00075300h
15141312111098
TENMS
R-00075300h
76543210
TENMS
R-00075300h
Table 3-108 STCR Register Field Descriptions
BitFieldTypeResetDescription
31NOREFR1hReads as one. Indicates that no separate reference clock is provided.
30SKEWR1hReads as one. The calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock.
29-24RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
23-0TENMSR00075300hAn optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. The value read is valid only when core clock is at 48MHz.

3.7.4.7 NVIC_ISER0 Register (Offset = 100h) [Reset = 00000000h]

NVIC_ISER0 is shown in Figure 3-77 and described in Table 3-109.

Return to the Summary Table.

Irq 0 to 31 Set Enable
This register is used to enable interrupts and determine which interrupts are currently enabled.

Figure 3-77 NVIC_ISER0 Register
3130292827262524
SETENA31SETENA30SETENA29SETENA28SETENA27SETENA26SETENA25SETENA24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
SETENA23SETENA22SETENA21SETENA20SETENA19SETENA18SETENA17SETENA16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
SETENA15SETENA14SETENA13SETENA12SETENA11SETENA10SETENA9SETENA8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
SETENA7SETENA6SETENA5SETENA4SETENA3SETENA2SETENA1SETENA0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-109 NVIC_ISER0 Register Field Descriptions
BitFieldTypeResetDescription
31SETENA31R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state.
30SETENA30R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state.
29SETENA29R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state.
28SETENA28R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state.
27SETENA27R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state.
26SETENA26R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state.
25SETENA25R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state.
24SETENA24R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state.
23SETENA23R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state.
22SETENA22R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state.
21SETENA21R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state.
20SETENA20R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state.
19SETENA19R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state.
18SETENA18R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state.
17SETENA17R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state.
16SETENA16R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state.
15SETENA15R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state.
14SETENA14R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state.
13SETENA13R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state.
12SETENA12R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state.
11SETENA11R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state.
10SETENA10R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state.
9SETENA9R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state.
8SETENA8R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state.
7SETENA7R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state.
6SETENA6R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state.
5SETENA5R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state.
4SETENA4R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state.
3SETENA3R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state.
2SETENA2R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state.
1SETENA1R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state.
0SETENA0R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state.

3.7.4.8 NVIC_ISER1 Register (Offset = 104h) [Reset = 00000000h]

NVIC_ISER1 is shown in Figure 3-78 and described in Table 3-110.

Return to the Summary Table.

Irq 32 to 63 Set Enable
This register is used to enable interrupts and determine which interrupts are currently enabled.

Figure 3-78 NVIC_ISER1 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSETENA37SETENA36SETENA35SETENA34SETENA33SETENA32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-110 NVIC_ISER1 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5SETENA37R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current enable state.
4SETENA36R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current enable state.
3SETENA35R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current enable state.
2SETENA34R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current enable state.
1SETENA33R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current enable state.
0SETENA32R/W0hWriting 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state.

3.7.4.9 NVIC_ICER0 Register (Offset = 180h) [Reset = 00000000h]

NVIC_ICER0 is shown in Figure 3-79 and described in Table 3-111.

Return to the Summary Table.

Irq 0 to 31 Clear Enable
This register is used to disable interrupts and determine which interrupts are currently enabled.

Figure 3-79 NVIC_ICER0 Register
3130292827262524
CLRENA31CLRENA30CLRENA29CLRENA28CLRENA27CLRENA26CLRENA25CLRENA24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CLRENA23CLRENA22CLRENA21CLRENA20CLRENA19CLRENA18CLRENA17CLRENA16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CLRENA15CLRENA14CLRENA13CLRENA12CLRENA11CLRENA10CLRENA9CLRENA8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CLRENA7CLRENA6CLRENA5CLRENA4CLRENA3CLRENA2CLRENA1CLRENA0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-111 NVIC_ICER0 Register Field Descriptions
BitFieldTypeResetDescription
31CLRENA31R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state.
30CLRENA30R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state.
29CLRENA29R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state.
28CLRENA28R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state.
27CLRENA27R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state.
26CLRENA26R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state.
25CLRENA25R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state.
24CLRENA24R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state.
23CLRENA23R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state.
22CLRENA22R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state.
21CLRENA21R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state.
20CLRENA20R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state.
19CLRENA19R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state.
18CLRENA18R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state.
17CLRENA17R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state.
16CLRENA16R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state.
15CLRENA15R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state.
14CLRENA14R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state.
13CLRENA13R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state.
12CLRENA12R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state.
11CLRENA11R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state.
10CLRENA10R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state.
9CLRENA9R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state.
8CLRENA8R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state.
7CLRENA7R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state.
6CLRENA6R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state.
5CLRENA5R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state.
4CLRENA4R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state.
3CLRENA3R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state.
2CLRENA2R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state.
1CLRENA1R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state.
0CLRENA0R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state.

3.7.4.10 NVIC_ICER1 Register (Offset = 184h) [Reset = 00000000h]

NVIC_ICER1 is shown in Figure 3-80 and described in Table 3-112.

Return to the Summary Table.

Irq 32 to 63 Clear Enable
This register is used to disable interrupts and determine which interrupts are currently enabled.

Figure 3-80 NVIC_ICER1 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCLRENA37CLRENA36CLRENA35CLRENA34CLRENA33CLRENA32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-112 NVIC_ICER1 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5CLRENA37R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current enable state.
4CLRENA36R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current enable state.
3CLRENA35R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current enable state.
2CLRENA34R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current enable state.
1CLRENA33R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current enable state.
0CLRENA32R/W0hWriting 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state.

3.7.4.11 NVIC_ISPR0 Register (Offset = 200h) [Reset = 00000000h]

NVIC_ISPR0 is shown in Figure 3-81 and described in Table 3-113.

Return to the Summary Table.

Irq 0 to 31 Set Pending
This register is used to force interrupts into the pending state and determine which interrupts are currently pending.

Figure 3-81 NVIC_ISPR0 Register
3130292827262524
SETPEND31SETPEND30SETPEND29SETPEND28SETPEND27SETPEND26SETPEND25SETPEND24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
SETPEND23SETPEND22SETPEND21SETPEND20SETPEND19SETPEND18SETPEND17SETPEND16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
SETPEND15SETPEND14SETPEND13SETPEND12SETPEND11SETPEND10SETPEND9SETPEND8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
SETPEND7SETPEND6SETPEND5SETPEND4SETPEND3SETPEND2SETPEND1SETPEND0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-113 NVIC_ISPR0 Register Field Descriptions
BitFieldTypeResetDescription
31SETPEND31R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state.
30SETPEND30R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state.
29SETPEND29R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state.
28SETPEND28R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state.
27SETPEND27R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state.
26SETPEND26R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state.
25SETPEND25R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state.
24SETPEND24R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state.
23SETPEND23R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state.
22SETPEND22R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state.
21SETPEND21R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state.
20SETPEND20R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state.
19SETPEND19R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state.
18SETPEND18R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state.
17SETPEND17R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state.
16SETPEND16R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state.
15SETPEND15R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state.
14SETPEND14R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state.
13SETPEND13R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state.
12SETPEND12R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state.
11SETPEND11R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state.
10SETPEND10R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state.
9SETPEND9R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state.
8SETPEND8R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state.
7SETPEND7R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state.
6SETPEND6R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state.
5SETPEND5R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state.
4SETPEND4R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state.
3SETPEND3R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state.
2SETPEND2R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state.
1SETPEND1R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state.
0SETPEND0R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state.

3.7.4.12 NVIC_ISPR1 Register (Offset = 204h) [Reset = 00000000h]

NVIC_ISPR1 is shown in Figure 3-82 and described in Table 3-114.

Return to the Summary Table.

Irq 32 to 63 Set Pending
This register is used to force interrupts into the pending state and determine which interrupts are currently pending.

Figure 3-82 NVIC_ISPR1 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSETPEND37SETPEND36SETPEND35SETPEND34SETPEND33SETPEND32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-114 NVIC_ISPR1 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5SETPEND37R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current state.
4SETPEND36R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current state.
3SETPEND35R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current state.
2SETPEND34R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current state.
1SETPEND33R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current state.
0SETPEND32R/W0hWriting 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state.

3.7.4.13 NVIC_ICPR0 Register (Offset = 280h) [Reset = 00000000h]

NVIC_ICPR0 is shown in Figure 3-83 and described in Table 3-115.

Return to the Summary Table.

Irq 0 to 31 Clear Pending
This register is used to clear pending interrupts and determine which interrupts are currently pending.

Figure 3-83 NVIC_ICPR0 Register
3130292827262524
CLRPEND31CLRPEND30CLRPEND29CLRPEND28CLRPEND27CLRPEND26CLRPEND25CLRPEND24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CLRPEND23CLRPEND22CLRPEND21CLRPEND20CLRPEND19CLRPEND18CLRPEND17CLRPEND16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CLRPEND15CLRPEND14CLRPEND13CLRPEND12CLRPEND11CLRPEND10CLRPEND9CLRPEND8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CLRPEND7CLRPEND6CLRPEND5CLRPEND4CLRPEND3CLRPEND2CLRPEND1CLRPEND0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-115 NVIC_ICPR0 Register Field Descriptions
BitFieldTypeResetDescription
31CLRPEND31R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state.
30CLRPEND30R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state.
29CLRPEND29R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state.
28CLRPEND28R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state.
27CLRPEND27R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state.
26CLRPEND26R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state.
25CLRPEND25R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state.
24CLRPEND24R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state.
23CLRPEND23R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state.
22CLRPEND22R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state.
21CLRPEND21R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state.
20CLRPEND20R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state.
19CLRPEND19R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state.
18CLRPEND18R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state.
17CLRPEND17R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state.
16CLRPEND16R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state.
15CLRPEND15R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state.
14CLRPEND14R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state.
13CLRPEND13R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state.
12CLRPEND12R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state.
11CLRPEND11R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state.
10CLRPEND10R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state.
9CLRPEND9R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state.
8CLRPEND8R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state.
7CLRPEND7R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state.
6CLRPEND6R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state.
5CLRPEND5R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state.
4CLRPEND4R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state.
3CLRPEND3R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state.
2CLRPEND2R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state.
1CLRPEND1R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state.
0CLRPEND0R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state.

3.7.4.14 NVIC_ICPR1 Register (Offset = 284h) [Reset = 00000000h]

NVIC_ICPR1 is shown in Figure 3-84 and described in Table 3-116.

Return to the Summary Table.

Irq 32 to 63 Clear Pending
This register is used to clear pending interrupts and determine which interrupts are currently pending.

Figure 3-84 NVIC_ICPR1 Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCLRPEND37CLRPEND36CLRPEND35CLRPEND34CLRPEND33CLRPEND32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-116 NVIC_ICPR1 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5CLRPEND37R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current state.
4CLRPEND36R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current state.
3CLRPEND35R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current state.
2CLRPEND34R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current state.
1CLRPEND33R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current state.
0CLRPEND32R/W0hWriting 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state.

3.7.4.15 NVIC_IABR0 Register (Offset = 300h) [Reset = 00000000h]

NVIC_IABR0 is shown in Figure 3-85 and described in Table 3-117.

Return to the Summary Table.

Irq 0 to 31 Active Bit
This register is used to determine which interrupts are active. Each flag in the register corresponds to one interrupt.

Figure 3-85 NVIC_IABR0 Register
3130292827262524
ACTIVE31ACTIVE30ACTIVE29ACTIVE28ACTIVE27ACTIVE26ACTIVE25ACTIVE24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
ACTIVE23ACTIVE22ACTIVE21ACTIVE20ACTIVE19ACTIVE18ACTIVE17ACTIVE16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
ACTIVE15ACTIVE14ACTIVE13ACTIVE12ACTIVE11ACTIVE10ACTIVE9ACTIVE8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
ACTIVE7ACTIVE6ACTIVE5ACTIVE4ACTIVE3ACTIVE2ACTIVE1ACTIVE0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 3-117 NVIC_IABR0 Register Field Descriptions
BitFieldTypeResetDescription
31ACTIVE31R0hReading 0 from this bit implies that interrupt line 31 is not active. Reading 1 from this bit implies that the interrupt line 31 is active (See EVENT:CPUIRQSEL31.EV for details).
30ACTIVE30R0hReading 0 from this bit implies that interrupt line 30 is not active. Reading 1 from this bit implies that the interrupt line 30 is active (See EVENT:CPUIRQSEL30.EV for details).
29ACTIVE29R0hReading 0 from this bit implies that interrupt line 29 is not active. Reading 1 from this bit implies that the interrupt line 29 is active (See EVENT:CPUIRQSEL29.EV for details).
28ACTIVE28R0hReading 0 from this bit implies that interrupt line 28 is not active. Reading 1 from this bit implies that the interrupt line 28 is active (See EVENT:CPUIRQSEL28.EV for details).
27ACTIVE27R0hReading 0 from this bit implies that interrupt line 27 is not active. Reading 1 from this bit implies that the interrupt line 27 is active (See EVENT:CPUIRQSEL27.EV for details).
26ACTIVE26R0hReading 0 from this bit implies that interrupt line 26 is not active. Reading 1 from this bit implies that the interrupt line 26 is active (See EVENT:CPUIRQSEL26.EV for details).
25ACTIVE25R0hReading 0 from this bit implies that interrupt line 25 is not active. Reading 1 from this bit implies that the interrupt line 25 is active (See EVENT:CPUIRQSEL25.EV for details).
24ACTIVE24R0hReading 0 from this bit implies that interrupt line 24 is not active. Reading 1 from this bit implies that the interrupt line 24 is active (See EVENT:CPUIRQSEL24.EV for details).
23ACTIVE23R0hReading 0 from this bit implies that interrupt line 23 is not active. Reading 1 from this bit implies that the interrupt line 23 is active (See EVENT:CPUIRQSEL23.EV for details).
22ACTIVE22R0hReading 0 from this bit implies that interrupt line 22 is not active. Reading 1 from this bit implies that the interrupt line 22 is active (See EVENT:CPUIRQSEL22.EV for details).
21ACTIVE21R0hReading 0 from this bit implies that interrupt line 21 is not active. Reading 1 from this bit implies that the interrupt line 21 is active (See EVENT:CPUIRQSEL21.EV for details).
20ACTIVE20R0hReading 0 from this bit implies that interrupt line 20 is not active. Reading 1 from this bit implies that the interrupt line 20 is active (See EVENT:CPUIRQSEL20.EV for details).
19ACTIVE19R0hReading 0 from this bit implies that interrupt line 19 is not active. Reading 1 from this bit implies that the interrupt line 19 is active (See EVENT:CPUIRQSEL19.EV for details).
18ACTIVE18R0hReading 0 from this bit implies that interrupt line 18 is not active. Reading 1 from this bit implies that the interrupt line 18 is active (See EVENT:CPUIRQSEL18.EV for details).
17ACTIVE17R0hReading 0 from this bit implies that interrupt line 17 is not active. Reading 1 from this bit implies that the interrupt line 17 is active (See EVENT:CPUIRQSEL17.EV for details).
16ACTIVE16R0hReading 0 from this bit implies that interrupt line 16 is not active. Reading 1 from this bit implies that the interrupt line 16 is active (See EVENT:CPUIRQSEL16.EV for details).
15ACTIVE15R0hReading 0 from this bit implies that interrupt line 15 is not active. Reading 1 from this bit implies that the interrupt line 15 is active (See EVENT:CPUIRQSEL15.EV for details).
14ACTIVE14R0hReading 0 from this bit implies that interrupt line 14 is not active. Reading 1 from this bit implies that the interrupt line 14 is active (See EVENT:CPUIRQSEL14.EV for details).
13ACTIVE13R0hReading 0 from this bit implies that interrupt line 13 is not active. Reading 1 from this bit implies that the interrupt line 13 is active (See EVENT:CPUIRQSEL13.EV for details).
12ACTIVE12R0hReading 0 from this bit implies that interrupt line 12 is not active. Reading 1 from this bit implies that the interrupt line 12 is active (See EVENT:CPUIRQSEL12.EV for details).
11ACTIVE11R0hReading 0 from this bit implies that interrupt line 11 is not active. Reading 1 from this bit implies that the interrupt line 11 is active (See EVENT:CPUIRQSEL11.EV for details).
10ACTIVE10R0hReading 0 from this bit implies that interrupt line 10 is not active. Reading 1 from this bit implies that the interrupt line 10 is active (See EVENT:CPUIRQSEL10.EV for details).
9ACTIVE9R0hReading 0 from this bit implies that interrupt line 9 is not active. Reading 1 from this bit implies that the interrupt line 9 is active (See EVENT:CPUIRQSEL9.EV for details).
8ACTIVE8R0hReading 0 from this bit implies that interrupt line 8 is not active. Reading 1 from this bit implies that the interrupt line 8 is active (See EVENT:CPUIRQSEL8.EV for details).
7ACTIVE7R0hReading 0 from this bit implies that interrupt line 7 is not active. Reading 1 from this bit implies that the interrupt line 7 is active (See EVENT:CPUIRQSEL7.EV for details).
6ACTIVE6R0hReading 0 from this bit implies that interrupt line 6 is not active. Reading 1 from this bit implies that the interrupt line 6 is active (See EVENT:CPUIRQSEL6.EV for details).
5ACTIVE5R0hReading 0 from this bit implies that interrupt line 5 is not active. Reading 1 from this bit implies that the interrupt line 5 is active (See EVENT:CPUIRQSEL5.EV for details).
4ACTIVE4R0hReading 0 from this bit implies that interrupt line 4 is not active. Reading 1 from this bit implies that the interrupt line 4 is active (See EVENT:CPUIRQSEL4.EV for details).
3ACTIVE3R0hReading 0 from this bit implies that interrupt line 3 is not active. Reading 1 from this bit implies that the interrupt line 3 is active (See EVENT:CPUIRQSEL3.EV for details).
2ACTIVE2R0hReading 0 from this bit implies that interrupt line 2 is not active. Reading 1 from this bit implies that the interrupt line 2 is active (See EVENT:CPUIRQSEL2.EV for details).
1ACTIVE1R0hReading 0 from this bit implies that interrupt line 1 is not active. Reading 1 from this bit implies that the interrupt line 1 is active (See EVENT:CPUIRQSEL1.EV for details).
0ACTIVE0R0hReading 0 from this bit implies that interrupt line 0 is not active. Reading 1 from this bit implies that the interrupt line 0 is active (See EVENT:CPUIRQSEL0.EV for details).

3.7.4.16 NVIC_IABR1 Register (Offset = 304h) [Reset = 00000000h]

NVIC_IABR1 is shown in Figure 3-86 and described in Table 3-118.

Return to the Summary Table.

Irq 32 to 63 Active Bit
This register is used to determine which interrupts are active. Each flag in the register corresponds to one interrupt.

Figure 3-86 NVIC_IABR1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDACTIVE37ACTIVE36ACTIVE35ACTIVE34ACTIVE33ACTIVE32
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 3-118 NVIC_IABR1 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5ACTIVE37R0hReading 0 from this bit implies that interrupt line 37 is not active. Reading 1 from this bit implies that the interrupt line 37 is active (See EVENT:CPUIRQSEL37.EV for details).
4ACTIVE36R0hReading 0 from this bit implies that interrupt line 36 is not active. Reading 1 from this bit implies that the interrupt line 36 is active (See EVENT:CPUIRQSEL36.EV for details).
3ACTIVE35R0hReading 0 from this bit implies that interrupt line 35 is not active. Reading 1 from this bit implies that the interrupt line 35 is active (See EVENT:CPUIRQSEL35.EV for details).
2ACTIVE34R0hReading 0 from this bit implies that interrupt line 34 is not active. Reading 1 from this bit implies that the interrupt line 34 is active (See EVENT:CPUIRQSEL34.EV for details).
1ACTIVE33R0hReading 0 from this bit implies that interrupt line 33 is not active. Reading 1 from this bit implies that the interrupt line 33 is active (See EVENT:CPUIRQSEL33.EV for details).
0ACTIVE32R0hReading 0 from this bit implies that interrupt line 32 is not active. Reading 1 from this bit implies that the interrupt line 32 is active (See EVENT:CPUIRQSEL32.EV for details).

3.7.4.17 NVIC_IPR0 Register (Offset = 400h) [Reset = 00000000h]

NVIC_IPR0 is shown in Figure 3-87 and described in Table 3-119.

Return to the Summary Table.

Irq 0 to 3 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 3-87 NVIC_IPR0 Register
313029282726252423222120191817161514131211109876543210
PRI_3PRI_2PRI_1PRI_0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-119 NVIC_IPR0 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_3R/W0hPriority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details).
23-16PRI_2R/W0hPriority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details).
15-8PRI_1R/W0hPriority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details).
7-0PRI_0R/W0hPriority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details).

3.7.4.18 NVIC_IPR1 Register (Offset = 404h) [Reset = 00000000h]

NVIC_IPR1 is shown in Figure 3-88 and described in Table 3-120.

Return to the Summary Table.

Irq 4 to 7 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 3-88 NVIC_IPR1 Register
313029282726252423222120191817161514131211109876543210
PRI_7PRI_6PRI_5PRI_4
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-120 NVIC_IPR1 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_7R/W0hPriority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details).
23-16PRI_6R/W0hPriority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details).
15-8PRI_5R/W0hPriority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details).
7-0PRI_4R/W0hPriority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details).

3.7.4.19 NVIC_IPR2 Register (Offset = 408h) [Reset = 00000000h]

NVIC_IPR2 is shown in Figure 3-89 and described in Table 3-121.

Return to the Summary Table.

Irq 8 to 11 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 3-89 NVIC_IPR2 Register
313029282726252423222120191817161514131211109876543210
PRI_11PRI_10PRI_9PRI_8
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-121 NVIC_IPR2 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_11R/W0hPriority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details).
23-16PRI_10R/W0hPriority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details).
15-8PRI_9R/W0hPriority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details).
7-0PRI_8R/W0hPriority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details).

3.7.4.20 NVIC_IPR3 Register (Offset = 40Ch) [Reset = 00000000h]

NVIC_IPR3 is shown in Figure 3-90 and described in Table 3-122.

Return to the Summary Table.

Irq 12 to 15 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 3-90 NVIC_IPR3 Register
313029282726252423222120191817161514131211109876543210
PRI_15PRI_14PRI_13PRI_12
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-122 NVIC_IPR3 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_15R/W0hPriority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details).
23-16PRI_14R/W0hPriority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details).
15-8PRI_13R/W0hPriority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details).
7-0PRI_12R/W0hPriority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details).

3.7.4.21 NVIC_IPR4 Register (Offset = 410h) [Reset = 00000000h]

NVIC_IPR4 is shown in Figure 3-91 and described in Table 3-123.

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Irq 16 to 19 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 3-91 NVIC_IPR4 Register
313029282726252423222120191817161514131211109876543210
PRI_19PRI_18PRI_17PRI_16
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-123 NVIC_IPR4 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_19R/W0hPriority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details).
23-16PRI_18R/W0hPriority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details).
15-8PRI_17R/W0hPriority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details).
7-0PRI_16R/W0hPriority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details).

3.7.4.22 NVIC_IPR5 Register (Offset = 414h) [Reset = 00000000h]

NVIC_IPR5 is shown in Figure 3-92 and described in Table 3-124.

Return to the Summary Table.

Irq 20 to 23 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 3-92 NVIC_IPR5 Register
313029282726252423222120191817161514131211109876543210
PRI_23PRI_22PRI_21PRI_20
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-124 NVIC_IPR5 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_23R/W0hPriority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details).
23-16PRI_22R/W0hPriority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details).
15-8PRI_21R/W0hPriority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details).
7-0PRI_20R/W0hPriority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details).

3.7.4.23 NVIC_IPR6 Register (Offset = 418h) [Reset = 00000000h]

NVIC_IPR6 is shown in Figure 3-93 and described in Table 3-125.

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Irq 24 to 27 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 3-93 NVIC_IPR6 Register
313029282726252423222120191817161514131211109876543210
PRI_27PRI_26PRI_25PRI_24
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-125 NVIC_IPR6 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_27R/W0hPriority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details).
23-16PRI_26R/W0hPriority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details).
15-8PRI_25R/W0hPriority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details).
7-0PRI_24R/W0hPriority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details).

3.7.4.24 NVIC_IPR7 Register (Offset = 41Ch) [Reset = 00000000h]

NVIC_IPR7 is shown in Figure 3-94 and described in Table 3-126.

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Irq 28 to 31 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 3-94 NVIC_IPR7 Register
313029282726252423222120191817161514131211109876543210
PRI_31PRI_30PRI_29PRI_28
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-126 NVIC_IPR7 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_31R/W0hPriority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details).
23-16PRI_30R/W0hPriority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details).
15-8PRI_29R/W0hPriority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details).
7-0PRI_28R/W0hPriority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details).

3.7.4.25 NVIC_IPR8 Register (Offset = 420h) [Reset = 00000000h]

NVIC_IPR8 is shown in Figure 3-95 and described in Table 3-127.

Return to the Summary Table.

Irq 32 to 35 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 3-95 NVIC_IPR8 Register
313029282726252423222120191817161514131211109876543210
PRI_35PRI_34PRI_33PRI_32
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-127 NVIC_IPR8 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_35R/W0hPriority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details).
23-16PRI_34R/W0hPriority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details).
15-8PRI_33R/W0hPriority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details).
7-0PRI_32R/W0hPriority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details).

3.7.4.26 NVIC_IPR9 Register (Offset = 424h) [Reset = 00000000h]

NVIC_IPR9 is shown in Figure 3-96 and described in Table 3-128.

Return to the Summary Table.

Irq 32 to 35 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 3-96 NVIC_IPR9 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPRI_37PRI_36
R/W-0hR/W-0hR/W-0h
Table 3-128 NVIC_IPR9 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
15-8PRI_37R/W0hPriority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details).
7-0PRI_36R/W0hPriority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details).

3.7.4.27 CPUID Register (Offset = D00h) [Reset = 410FC241h]

CPUID is shown in Figure 3-97 and described in Table 3-129.

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CPUID Base
This register determines the ID number of the processor core, the version number of the processor core and the implementation details of the processor core.

Figure 3-97 CPUID Register
31302928272625242322212019181716
IMPLEMENTERVARIANTCONSTANT
R-41hR-0hR-Fh
1514131211109876543210
PARTNOREVISION
R-C24hR-1h
Table 3-129 CPUID Register Field Descriptions
BitFieldTypeResetDescription
31-24IMPLEMENTERR41hImplementor code.
23-20VARIANTR0hImplementation defined variant number.
19-16CONSTANTRFhReads as 0xF
15-4PARTNORC24hNumber of processor within family.
3-0REVISIONR1hImplementation defined revision number.

3.7.4.28 ICSR Register (Offset = D04h) [Reset = 00000000h]

ICSR is shown in Figure 3-98 and described in Table 3-130.

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Interrupt Control State
This register is used to set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, and check the vector number of the active exception.

Figure 3-98 ICSR Register
3130292827262524
NMIPENDSETRESERVEDPENDSVSETPENDSVCLRPENDSTSETPENDSTCLRRESERVED
R/W-0hR/W-0hR/W-0hW-XR/W-0hW-XR-0h
2322212019181716
ISRPREEMPTISRPENDINGRESERVEDVECTPENDING
R-0hR-0hR-0hR-0h
15141312111098
VECTPENDINGRETTOBASERESERVEDVECTACTIVE
R-0hR-0hR-0hR-0h
76543210
VECTACTIVE
R-0h
Table 3-130 ICSR Register Field Descriptions
BitFieldTypeResetDescription
31NMIPENDSETR/W0hSet pending NMI bit. Setting this bit pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers.
0: No action
1: Set pending NMI
30-29RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28PENDSVSETR/W0hSet pending pendSV bit.
0: No action
1: Set pending PendSV
27PENDSVCLRWXClear pending pendSV bit
0: No action
1: Clear pending pendSV
26PENDSTSETR/W0hSet a pending SysTick bit.
0: No action
1: Set pending SysTick
25PENDSTCLRWXClear pending SysTick bit
0: No action
1: Clear pending SysTick
24RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
23ISRPREEMPTR0hThis field can only be used at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, the interrupt is serviced.
0: A pending exception is not serviced.
1: A pending exception is serviced on exit from the debug halt state
22ISRPENDINGR0hInterrupt pending flag. Excludes NMI and faults.
0x0: Interrupt not pending
0x1: Interrupt pending
21-18RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
17-12VECTPENDINGR0hPending ISR number field. This field contains the interrupt number of the highest priority pending ISR.
11RETTOBASER0hIndicates whether there are preempted active exceptions:
0: There are preempted active exceptions to execute
1: There are no active exceptions, or the currently-executing exception is the only active exception.
10-9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8-0VECTACTIVER0hActive ISR number field. Reset clears this field.

3.7.4.29 VTOR Register (Offset = D08h) [Reset = 00000000h]

VTOR is shown in Figure 3-99 and described in Table 3-131.

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Vector Table Offset
This register is used to relocated the vector table base address. The vector table base offset determines the offset from the bottom of the memory map. The two most significant bits and the seven least significant bits of the vector table base offset must be 0. The portion of vector table base offset that is allowed to change is TBLOFF.

Figure 3-99 VTOR Register
3130292827262524
RESERVEDTBLOFF
R/W-0hR/W-0h
2322212019181716
TBLOFF
R/W-0h
15141312111098
TBLOFF
R/W-0h
76543210
TBLOFFRESERVED
R/W-0hR/W-0h
Table 3-131 VTOR Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
29-7TBLOFFR/W0hBits 29 down to 7 of the vector table base offset.
6-0RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.30 AIRCR Register (Offset = D0Ch) [Reset = FA050000h]

AIRCR is shown in Figure 3-100 and described in Table 3-132.

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Application Interrupt/Reset Control
This register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).

Figure 3-100 AIRCR Register
3130292827262524
VECTKEY
R/W-FA05h
2322212019181716
VECTKEY
R/W-FA05h
15141312111098
ENDIANESSRESERVEDPRIGROUP
R-0hR-0hR/W-0h
76543210
RESERVEDSYSRESETREQVECTCLRACTIVEVECTRESET
R/W-0hW-0hW-0hW-0h
Table 3-132 AIRCR Register Field Descriptions
BitFieldTypeResetDescription
31-16VECTKEYR/WFA05hRegister key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05.
15ENDIANESSR0hData endianness bit
0h = Little endian
1h = Big endian
14-11RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
10-8PRIGROUPR/W0hInterrupt priority grouping field. This field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices.
7-3RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2SYSRESETREQW0hRequests a warm reset. Setting this bit does not prevent Halting Debug from running.
1VECTCLRACTIVEW0hClears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. This bit is for returning to a known state during debug. The bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set.
0VECTRESETW0hSystem Reset bit. Resets the system, with the exception of debug components. This bit is reserved for debug use and can be written to 1 only when the core is halted. The bit self-clears. Writing this bit to 1 while core is not halted may result in unpredictable behavior.

3.7.4.31 SCR Register (Offset = D10h) [Reset = 00000000h]

SCR is shown in Figure 3-101 and described in Table 3-133.

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System Control
This register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states.

Figure 3-101 SCR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSEVONPENDRESERVEDSLEEPDEEPSLEEPONEXITRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-133 SCR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4SEVONPENDR/W0hSend Event on Pending bit:
0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If
the processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
3RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2SLEEPDEEPR/W0hControls whether the processor uses sleep or deep sleep as its low power mode
0h = Sleep
1h = Deep sleep
1SLEEPONEXITR/W0hSleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application.
0: Do not sleep when returning to thread mode
1: Sleep on ISR exit
0RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.32 CCR Register (Offset = D14h) [Reset = 00000200h]

CCR is shown in Figure 3-102 and described in Table 3-134.

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Configuration Control
This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault, trap divide by zero and unaligned accesses, enable user access to the Software Trigger Interrupt Register (STIR), control entry to Thread Mode.

Figure 3-102 CCR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDSTKALIGNBFHFNMIGN
R/W-0hR/W-1hR/W-0h
76543210
RESERVEDDIV_0_TRPUNALIGN_TRPRESERVEDUSERSETMPENDNONBASETHREDENA
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-134 CCR Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9STKALIGNR/W1hStack alignment bit.
0: Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.
1: On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return.
8BFHFNMIGNR/W0hEnables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the HardFault, NMI, and FAULTMASK escalated handlers:
0: Data BusFaults caused by load and store instructions cause a lock-up
1: Data BusFaults caused by load and store instructions are ignored.
Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use
of this bit is to probe system devices and bridges to detect problems.
7-5RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4DIV_0_TRPR/W0hEnables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
0: Do not trap divide by 0. In this mode, a divide by zero returns a quotient of 0.
1: Trap divide by 0. The relevant Usage Fault Status Register bit is CFSR.DIVBYZERO.
3UNALIGN_TRPR/W0hEnables unaligned access traps:
0: Do not trap unaligned halfword and word accesses
1: Trap unaligned halfword and word accesses. The relevant Usage Fault Status Register bit is CFSR.UNALIGNED.
If this bit is set to 1, an unaligned access generates a UsageFault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the value in UNALIGN_TRP.
2RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1USERSETMPENDR/W0hEnables unprivileged software access to STIR:
0: User code is not allowed to write to the Software Trigger Interrupt register (STIR).
1: User code can write the Software Trigger Interrupt register (STIR) to trigger (pend) a Main exception, which is associated with the Main stack pointer.
0NONBASETHREDENAR/W0hIndicates how the processor enters Thread mode:
0: Processor can enter Thread mode only when no exception is active.
1: Processor can enter Thread mode from any level using the appropriate return value (EXC_RETURN).
Exception returns occur when one of the following instructions loads a value of 0xFXXXXXXX into the PC while in Handler mode:
- POP/LDM which includes loading the PC.
- LDR with PC as a destination.
- BX with any register.
The value written to the PC is intercepted and is referred to as the EXC_RETURN value.

3.7.4.33 SHPR1 Register (Offset = D18h) [Reset = 00000000h]

SHPR1 is shown in Figure 3-103 and described in Table 3-135.

Return to the Summary Table.

System Handlers 4-7 Priority
This register is used to prioritize the following system handlers: Memory manage, Bus fault, and Usage fault. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.

Figure 3-103 SHPR1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPRI_6PRI_5PRI_4
R-0hR/W-0hR/W-0hR/W-0h
Table 3-135 SHPR1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16PRI_6R/W0hPriority of system handler 6. UsageFault
15-8PRI_5R/W0hPriority of system handler 5: BusFault
7-0PRI_4R/W0hPriority of system handler 4: MemManage

3.7.4.34 SHPR2 Register (Offset = D1Ch) [Reset = 00000000h]

SHPR2 is shown in Figure 3-104 and described in Table 3-136.

Return to the Summary Table.

System Handlers 8-11 Priority
This register is used to prioritize the SVC handler. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.

Figure 3-104 SHPR2 Register
313029282726252423222120191817161514131211109876543210
PRI_11RESERVED
R/W-0hR-0h
Table 3-136 SHPR2 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_11R/W0hPriority of system handler 11. SVCall
23-0RESERVEDR0hReserved

3.7.4.35 SHPR3 Register (Offset = D20h) [Reset = 00000000h]

SHPR3 is shown in Figure 3-105 and described in Table 3-137.

Return to the Summary Table.

System Handlers 12-15 Priority
This register is used to prioritize the following system handlers: SysTick, PendSV and Debug Monitor. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.

Figure 3-105 SHPR3 Register
313029282726252423222120191817161514131211109876543210
PRI_15PRI_14RESERVEDPRI_12
R/W-0hR/W-0hR-0hR/W-0h
Table 3-137 SHPR3 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_15R/W0hPriority of system handler 15. SysTick exception
23-16PRI_14R/W0hPriority of system handler 14. Pend SV
15-8RESERVEDR0hReserved
7-0PRI_12R/W0hPriority of system handler 12. Debug Monitor

3.7.4.36 SHCSR Register (Offset = D24h) [Reset = 00000000h]

SHCSR is shown in Figure 3-106 and described in Table 3-138.

Return to the Summary Table.

System Handler Control and State
This register is used to enable or disable the system handlers, determine the pending status of bus fault, mem manage fault, and SVC, determine the active status of the system handlers. If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard Fault.

Figure 3-106 SHCSR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDUSGFAULTENABUSFAULTENAMEMFAULTENA
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
SVCALLPENDEDBUSFAULTPENDEDMEMFAULTPENDEDUSGFAULTPENDEDSYSTICKACTPENDSVACTRESERVEDMONITORACT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
SVCALLACTRESERVEDUSGFAULTACTRESERVEDBUSFAULTACTMEMFAULTACT
R-0hR-0hR-0hR-0hR-0hR-0h
Table 3-138 SHCSR Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
18USGFAULTENAR/W0hUsage fault system handler enable
0h = Exception disabled
1h = Exception enabled
17BUSFAULTENAR/W0hBus fault system handler enable
0h = Exception disabled
1h = Exception enabled
16MEMFAULTENAR/W0hMemManage fault system handler enable
0h = Exception disabled
1h = Exception enabled
15SVCALLPENDEDR0hSVCall pending
0h = Exception is not active
1h = Exception is pending.
14BUSFAULTPENDEDR0hBusFault pending
0h = Exception is not active
1h = Exception is pending.
13MEMFAULTPENDEDR0hMemManage exception pending
0h = Exception is not active
1h = Exception is pending.
12USGFAULTPENDEDR0hUsage fault pending
0h = Exception is not active
1h = Exception is pending.
11SYSTICKACTR0hSysTick active flag.
0x0: Not active
0x1: Active
0h = Exception is not active
1h = Exception is active
10PENDSVACTR0hPendSV active
0x0: Not active
0x1: Active
9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8MONITORACTR0hDebug monitor active
0h = Exception is not active
1h = Exception is active
7SVCALLACTR0hSVCall active
0h = Exception is not active
1h = Exception is active
6-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3USGFAULTACTR0hUsageFault exception active
0h = Exception is not active
1h = Exception is active
2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1BUSFAULTACTR0hBusFault exception active
0h = Exception is not active
1h = Exception is active
0MEMFAULTACTR0hMemManage exception active
0h = Exception is not active
1h = Exception is active

3.7.4.37 CFSR Register (Offset = D28h) [Reset = 00000000h]

CFSR is shown in Figure 3-107 and described in Table 3-139.

Return to the Summary Table.

Configurable Fault Status
This register is used to obtain information about local faults. These registers include three subsections: The first byte is Memory Manage Fault Status Register (MMFSR). The second byte is Bus Fault Status Register (BFSR). The higher half-word is Usage Fault Status Register (UFSR). The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit.
The CFSR is byte accessible. CFSR or its subregisters can be accessed as follows:
The following accesses are possible to the CFSR register:
- access the complete register with a word access to 0xE000ED28.
- access the MMFSR with a byte access to 0xE000ED28
- access the MMFSR and BFSR with a halfword access to 0xE000ED28
- access the BFSR with a byte access to 0xE000ED29
- access the UFSR with a halfword access to 0xE000ED2A.

Figure 3-107 CFSR Register
3130292827262524
RESERVEDDIVBYZEROUNALIGNED
R/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDNOCPINVPCINVSTATEUNDEFINSTR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BFARVALIDRESERVEDSTKERRUNSTKERRIMPRECISERRPRECISERRIBUSERR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
MMARVALIDRESERVEDMSTKERRMUNSTKERRRESERVEDDACCVIOLIACCVIOL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-139 CFSR Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
25DIVBYZEROR/W0hWhen CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0.
24UNALIGNEDR/W0hWhen CCR.UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of CCR.UNALIGN_TRP.
23-20RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
19NOCPR/W0hAttempt to use a coprocessor instruction. The processor does not support coprocessor instructions.
18INVPCR/W0hAttempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC.
17INVSTATER/W0hIndicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state). This includes state change after entry to or return from exception, as well as from inter-working instructions. Return PC points to faulting instruction, with the invalid state.
16UNDEFINSTRR/W0hThis bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction.
15BFARVALIDR/W0hThis bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten.
14-13RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
12STKERRR/W0hStacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. BFAR is not written.
11UNSTKERRR/W0hUnstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. BFAR is not written.
10IMPRECISERRR/W0hImprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. BFAR is not written.
9PRECISERRR/W0hPrecise data bus error return.
8IBUSERRR/W0hInstruction bus error flag. This flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. BFAR is not written.
7MMARVALIDR/W0hMemory Manage Address Register (MMFAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMFAR value has been overwritten.
6-5RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4MSTKERRR/W0hStacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. MMFAR is not written.
3MUNSTKERRR/W0hUnstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. MMFAR is not written.
2RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1DACCVIOLR/W0hData access violation flag. Attempting to load or store at a location that does not permit the operation sets this flag. The return PC points to the faulting instruction. This error loads MMFAR with the address of the attempted access.
0IACCVIOLR/W0hInstruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets this flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written.

3.7.4.38 HFSR Register (Offset = D2Ch) [Reset = 00000000h]

HFSR is shown in Figure 3-108 and described in Table 3-140.

Return to the Summary Table.

Hard Fault Status
This register is used to obtain information about events that activate the Hard Fault handler. This register is a write-clear register. This means that writing a 1 to a bit clears that bit.

Figure 3-108 HFSR Register
3130292827262524
DEBUGEVTFORCEDRESERVED
R/W1C-0hR/W1C-0hR/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDVECTTBLRESERVED
R/W-0hR/W1C-0hR/W-0h
Table 3-140 HFSR Register Field Descriptions
BitFieldTypeResetDescription
31DEBUGEVTR/W1C0hThis bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated.
30FORCEDR/W1C0hHard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause.
29-2RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1VECTTBLR/W1C0hThis bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction.
0RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.39 DFSR Register (Offset = D30h) [Reset = 00000000h]

DFSR is shown in Figure 3-109 and described in Table 3-141.

Return to the Summary Table.

Debug Fault Status
This register is used to monitor external debug requests, vector catches, data watchpoint match, BKPT instruction execution, halt requests. Multiple flags in the Debug Fault Status Register can be set when multiple fault conditions occur. The register is read/write clear. This means that it can be read normally. Writing a 1 to a bit clears that bit. Note that these bits are not set unless the event is caught. This means that it causes a stop of some sort. If halting debug is enabled, these events stop the processor into debug. If debug is disabled and the debug monitor is enabled, then this becomes a debug monitor handler call, if priority permits. If debug and the monitor are both disabled, some of these events are Hard Faults, and some are ignored.

Figure 3-109 DFSR Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEXTERNALVCATCHDWTTRAPBKPTHALTED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-141 DFSR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4EXTERNALR/W0hExternal debug request flag. The processor stops on next instruction boundary.
0x0: External debug request signal not asserted
0x1: External debug request signal asserted
3VCATCHR/W0hVector catch flag. When this flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault.
0x0: No vector catch occurred
0x1: Vector catch occurred
2DWTTRAPR/W0hData Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction.
0x0: No DWT match
0x1: DWT match
1BKPTR/W0hBKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction.
0x0: No BKPT instruction execution
0x1: BKPT instruction execution
0HALTEDR/W0hHalt request flag. The processor is halted on the next instruction.
0x0: No halt request
0x1: Halt requested by NVIC, including step

3.7.4.40 MMFAR Register (Offset = D34h) [Reset = 00000000h]

MMFAR is shown in Figure 3-110 and described in Table 3-142.

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Mem Manage Fault Address
This register is used to read the address of the location that caused a Memory Manage Fault.

Figure 3-110 MMFAR Register
313029282726252423222120191817161514131211109876543210
ADDRESS
R/W-X
Table 3-142 MMFAR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/WXMem Manage fault address field.
This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination with CFSR.MMARVALIDindicate the cause of the fault.

3.7.4.41 BFAR Register (Offset = D38h) [Reset = 00000000h]

BFAR is shown in Figure 3-111 and described in Table 3-143.

Return to the Summary Table.

Bus Fault Address
This register is used to read the address of the location that generated a Bus Fault.

Figure 3-111 BFAR Register
313029282726252423222120191817161514131211109876543210
ADDRESS
R/W-X
Table 3-143 BFAR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/WXBus fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted.
Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the fault.

3.7.4.42 AFSR Register (Offset = D3Ch) [Reset = 00000000h]

AFSR is shown in Figure 3-112 and described in Table 3-144.

Return to the Summary Table.

Auxiliary Fault Status
This register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0.

Figure 3-112 AFSR Register
313029282726252423222120191817161514131211109876543210
IMPDEF
R/W-0h
Table 3-144 AFSR Register Field Descriptions
BitFieldTypeResetDescription
31-0IMPDEFR/W0hImplementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0

3.7.4.43 ID_PFR0 Register (Offset = D40h) [Reset = 00000030h]

ID_PFR0 is shown in Figure 3-113 and described in Table 3-145.

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Processor Feature 0

Figure 3-113 ID_PFR0 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSTATE1STATE0
R-0hR-3hR-0h
Table 3-145 ID_PFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-4STATE1R3hState1 (T-bit == 1)
0x0: N/A
0x1: N/A
0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.)
0x3: Thumb-2 encoding with all Thumb-2 basic instructions
3-0STATE0R0hState0 (T-bit == 0)
0x0: No ARM encoding
0x1: N/A

3.7.4.44 ID_PFR1 Register (Offset = D44h) [Reset = 00000200h]

ID_PFR1 is shown in Figure 3-114 and described in Table 3-146.

Return to the Summary Table.

Processor Feature 1

Figure 3-114 ID_PFR1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMICROCONTROLLER_PROGRAMMERS_MODEL
R-0hR-2h
76543210
RESERVED
R-0h
Table 3-146 ID_PFR1 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
11-8MICROCONTROLLER_PROGRAMMERS_MODELR2hMicrocontroller programmer's model
0x0: Not supported
0x2: Two-stack support
7-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.45 ID_DFR0 Register (Offset = D48h) [Reset = 00100000h]

ID_DFR0 is shown in Figure 3-115 and described in Table 3-147.

Return to the Summary Table.

Debug Feature 0
This register provides a high level view of the debug system. Further details are provided in the debug infrastructure itself.

Figure 3-115 ID_DFR0 Register
3130292827262524
RESERVED
R-0h
2322212019181716
MICROCONTROLLER_DEBUG_MODELRESERVED
R-1hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 3-147 ID_DFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
23-20MICROCONTROLLER_DEBUG_MODELR1hMicrocontroller Debug Model - memory mapped
0x0: Not supported
0x1: Microcontroller debug v1 (ITMv1 and DWTv1)
19-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.46 ID_AFR0 Register (Offset = D4Ch) [Reset = 00000000h]

ID_AFR0 is shown in Figure 3-116 and described in Table 3-148.

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Auxiliary Feature 0
This register provides some freedom for implementation defined features to be registered. Not used in Cortex-M.

Figure 3-116 ID_AFR0 Register
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 3-148 ID_AFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.47 ID_MMFR0 Register (Offset = D50h) [Reset = 00100030h]

ID_MMFR0 is shown in Figure 3-117 and described in Table 3-149.

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Memory Model Feature 0
General information on the memory model and memory management support.

Figure 3-117 ID_MMFR0 Register
313029282726252423222120191817161514131211109876543210
RESERVED
R-00100030h
Table 3-149 ID_MMFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR00100030hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.48 ID_MMFR1 Register (Offset = D54h) [Reset = 00000000h]

ID_MMFR1 is shown in Figure 3-118 and described in Table 3-150.

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Memory Model Feature 1
General information on the memory model and memory management support.

Figure 3-118 ID_MMFR1 Register
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 3-150 ID_MMFR1 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.49 ID_MMFR2 Register (Offset = D58h) [Reset = 01000000h]

ID_MMFR2 is shown in Figure 3-119 and described in Table 3-151.

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Memory Model Feature 2
General information on the memory model and memory management support.

Figure 3-119 ID_MMFR2 Register
3130292827262524
RESERVEDWAIT_FOR_INTERRUPT_STALLING
R-0hR-1h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 3-151 ID_MMFR2 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
24WAIT_FOR_INTERRUPT_STALLINGR1hwait for interrupt stalling
0x0: Not supported
0x1: Wait for interrupt supported
23-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.50 ID_MMFR3 Register (Offset = D5Ch) [Reset = 00000000h]

ID_MMFR3 is shown in Figure 3-120 and described in Table 3-152.

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Memory Model Feature 3
General information on the memory model and memory management support.

Figure 3-120 ID_MMFR3 Register
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 3-152 ID_MMFR3 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.51 ID_ISAR0 Register (Offset = D60h) [Reset = 01101110h]

ID_ISAR0 is shown in Figure 3-121 and described in Table 3-153.

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ISA Feature 0
Information on the instruction set attributes register

Figure 3-121 ID_ISAR0 Register
313029282726252423222120191817161514131211109876543210
RESERVED
R-01101110h
Table 3-153 ID_ISAR0 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR01101110hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.52 ID_ISAR1 Register (Offset = D64h) [Reset = 02112000h]

ID_ISAR1 is shown in Figure 3-122 and described in Table 3-154.

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ISA Feature 1
Information on the instruction set attributes register

Figure 3-122 ID_ISAR1 Register
313029282726252423222120191817161514131211109876543210
RESERVED
R-02112000h
Table 3-154 ID_ISAR1 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR02112000hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.53 ID_ISAR2 Register (Offset = D68h) [Reset = 21232231h]

ID_ISAR2 is shown in Figure 3-123 and described in Table 3-155.

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ISA Feature 2
Information on the instruction set attributes register

Figure 3-123 ID_ISAR2 Register
313029282726252423222120191817161514131211109876543210
RESERVED
R-21232231h
Table 3-155 ID_ISAR2 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR21232231hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.54 ID_ISAR3 Register (Offset = D6Ch) [Reset = 01111131h]

ID_ISAR3 is shown in Figure 3-124 and described in Table 3-156.

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ISA Feature 3
Information on the instruction set attributes register

Figure 3-124 ID_ISAR3 Register
313029282726252423222120191817161514131211109876543210
RESERVED
R-01111131h
Table 3-156 ID_ISAR3 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR01111131hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.55 ID_ISAR4 Register (Offset = D70h) [Reset = 01310132h]

ID_ISAR4 is shown in Figure 3-125 and described in Table 3-157.

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ISA Feature 4
Information on the instruction set attributes register

Figure 3-125 ID_ISAR4 Register
313029282726252423222120191817161514131211109876543210
RESERVED
R-01310132h
Table 3-157 ID_ISAR4 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR01310132hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.56 CPACR Register (Offset = D88h) [Reset = 00000000h]

CPACR is shown in Figure 3-126 and described in Table 3-158.

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Coprocessor Access Control
This register specifies the access privileges for coprocessors.

Figure 3-126 CPACR Register
313029282726252423222120191817161514131211109876543210
RESERVED
R/W-0h
Table 3-158 CPACR Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.7.4.57 MPU_TYPE Register (Offset = D90h) [Reset = 00000800h]

MPU_TYPE is shown in Figure 3-127 and described in Table 3-159.

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MPU Type
This register indicates many regions the MPU supports.

Figure 3-127 MPU_TYPE Register
3130292827262524
RESERVED
R-0h
2322212019181716
IREGION
R-0h
15141312111098
DREGION
R-8h
76543210
RESERVEDSEPARATE
R-0hR-0h
Table 3-159 MPU_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReads 0.
23-16IREGIONR0hThe processor core uses only a unified MPU, this field always reads 0x0.
15-8DREGIONR8hNumber of supported MPU regions field. This field reads 0x08 indicating eight MPU regions.
7-1RESERVEDR0hReads 0.
0SEPARATER0hThe processor core uses only a unified MPU, thus this field is always 0.

3.7.4.58 MPU_CTRL Register (Offset = D94h) [Reset = 00000000h]

MPU_CTRL is shown in Figure 3-128 and described in Table 3-160.

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MPU Control
This register is used to enable the MPU, enable the default memory map (background region), and enable the MPU when in Hard Fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. When the MPU is enabled, at least one region of the memory map must be enabled for the MPU to function unless the PRIVDEFENA bit is set. If the PRIVDEFENA bit is set and no regions are enabled, then only privileged code can operate. When the MPU is disabled, the default address map is used, as if no MPU is present. When the MPU is enabled, only the system partition and vector table loads are always accessible. Other areas are accessible based on regions and whether PRIVDEFENA is enabled. Unless HFNMIENA is set, the MPU is not enabled when the exception priority is -1 or -2. These priorities are only possible when in Hard fault, NMI, or when FAULTMASK is enabled. The HFNMIENA bit enables the MPU when operating with these two priorities.

Figure 3-128 MPU_CTRL Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDPRIVDEFENAHFNMIENAENABLE
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-160 MPU_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2PRIVDEFENAR/W0hThis bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. The background region acts as if it was region number 1 before any settable regions. Any region that is set up overlays this default map, and overrides it. If this bit is not set, the default memory map is disabled, and memory not covered by a region faults. This applies to memory type, Execute Never (XN), cache and shareable rules. However, this only applies to privileged mode (fetch and data access). User mode code faults unless a region has been set up for its code and data. When the MPU is disabled, the default map acts on both privileged and user mode code. XN and SO rules always apply to the system partition whether this enable is set or not. If the MPU is disabled, this bit is ignored.
1HFNMIENAR/W0hThis bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If this bit and ENABLE are set, the MPU is enabled when in these handlers. If this bit is not set, the MPU is disabled when in these handlers, regardless of the value of ENABLE bit. If this bit is set and ENABLE is not set, behavior is unpredictable.
0ENABLER/W0hEnable MPU
0: MPU disabled
1: MPU enabled

3.7.4.59 MPU_RNR Register (Offset = D98h) [Reset = 00000000h]

MPU_RNR is shown in Figure 3-129 and described in Table 3-161.

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MPU Region Number
This register is used to select which protection region is accessed. The following write to MPU_RASR or MPU_RBAR configures the characteristics of the protection region that is selected by this register.

Figure 3-129 MPU_RNR Register
313029282726252423222120191817161514131211109876543210
RESERVEDREGION
R/W-0hR/W-0h
Table 3-161 MPU_RNR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-0REGIONR/W0hRegion select field.
This field selects the region to operate on when using the MPU_RASR and MPU_RBAR. It must be written first except when the address MPU_RBAR.VALID and MPU_RBAR.REGION fields are written, which overwrites this.

3.7.4.60 MPU_RBAR Register (Offset = D9Ch) [Reset = 00000000h]

MPU_RBAR is shown in Figure 3-130 and described in Table 3-162.

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MPU Region Base Address
This register writes the base address of a region. It also contains a REGION field that can be used to override MPU_RNR.REGION, if the VALID bit is set. This register sets the base for the region. It is aligned by the size. So, a 64-KB sized region must be aligned on a multiple of 64KB, for example, 0x00010000 or 0x00020000. The region always reads back as the current MPU region number. VALID always reads back as 0. Writing VALID = 1 and REGION = n changes the region number to n. This is a short-hand way to write the MPU_RNR. This register is unpredictable if accessed other than as a word.

Figure 3-130 MPU_RBAR Register
3130292827262524
ADDR
R/W-0h
2322212019181716
ADDR
R/W-0h
15141312111098
ADDR
R/W-0h
76543210
ADDRVALIDREGION
R/W-0hR/W-0hR/W-0h
Table 3-162 MPU_RBAR Register Field Descriptions
BitFieldTypeResetDescription
31-5ADDRR/W0hRegion base address field.
The position of the LSB depends on the region size, so that the base address is aligned according to an even multiple of size. The power of 2 size specified by the SZENABLE field of the MPU Region Attribute and Size Register defines how many bits of base address are used.
4VALIDR/W0hMPU region number valid:
0: MPU_RNR remains unchanged and is interpreted.
1: MPU_RNR is overwritten by REGION.
3-0REGIONR/W0hMPU region override field

3.7.4.61 MPU_RASR Register (Offset = DA0h) [Reset = 00000000h]

MPU_RASR is shown in Figure 3-131 and described in Table 3-163.

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MPU Region Attribute and Size
This register controls the MPU access permissions. The register is made up of two part registers, each of halfword size. These can be accessed using the halfword size, or they can both be simultaneously accessed using a word operation. The sub-region disable bits are not supported for region sizes of 32 bytes, 64 bytes, and 128 bytes. When these region sizes are used, the subregion disable bits must be programmed as 0.

Figure 3-131 MPU_RASR Register
3130292827262524
RESERVEDXNRESERVEDAP
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDTEXSCB
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
SRD
R/W-0h
76543210
RESERVEDSIZEENABLE
R/W-0hR/W-0hR/W-0h
Table 3-163 MPU_RASR Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28XNR/W0hInstruction access disable:
0: Enable instruction fetches
1: Disable instruction fetches
27RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
26-24APR/W0hData access permission:
0x0: Priviliged permissions: No access. User permissions: No access.
0x1: Priviliged permissions: Read-write. User permissions: No access.
0x2: Priviliged permissions: Read-write. User permissions: Read-only.
0x3: Priviliged permissions: Read-write. User permissions: Read-write.
0x4: Reserved
0x5: Priviliged permissions: Read-only. User permissions: No access.
0x6: Priviliged permissions: Read-only. User permissions: Read-only.
0x7: Priviliged permissions: Read-only. User permissions: Read-only.
23-22RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
21-19TEXR/W0hType extension
18SR/W0hShareable bit:
0: Not shareable
1: Shareable
17CR/W0hCacheable bit:
0: Not cacheable
1: Cacheable
16BR/W0hBufferable bit:
0: Not bufferable
1: Bufferable
15-8SRDR/W0hSub-Region Disable field:
Setting a bit in this field disables the corresponding sub-region. Regions are split into eight equal-sized sub-regions. Sub-regions are not supported for region sizes of 128 bytes and less.
7-6RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5-1SIZER/W0hMPU Protection Region Size Field:
0x04: 32B
0x05: 64B
0x06: 128B
0x07: 256B
0x08: 512B
0x09: 1KB
0x0A: 2KB
0x0B: 4KB
0x0C: 8KB
0x0D: 16KB
0x0E: 32KB
0x0F: 64KB
0x10: 128KB
0x11: 256KB
0x12: 512KB
0x13: 1MB
0x14: 2MB
0x15: 4MB
0x16: 8MB
0x17: 16MB
0x18: 32MB
0x19: 64MB
0x1A: 128MB
0x1B: 256MB
0x1C: 512MB
0x1D: 1GB
0x1E: 2GB
0x1F: 4GB
0ENABLER/W0hRegion enable bit:
0: Disable region
1: Enable region

3.7.4.62 MPU_RBAR_A1 Register (Offset = DA4h) [Reset = 00000000h]

MPU_RBAR_A1 is shown in Figure 3-132 and described in Table 3-164.

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MPU Alias 1 Region Base Address
Alias for MPU_RBAR

Figure 3-132 MPU_RBAR_A1 Register
313029282726252423222120191817161514131211109876543210
MPU_RBAR_A1
R/W-0h
Table 3-164 MPU_RBAR_A1 Register Field Descriptions
BitFieldTypeResetDescription
31-0MPU_RBAR_A1R/W0hAlias for MPU_RBAR

3.7.4.63 MPU_RASR_A1 Register (Offset = DA8h) [Reset = 00000000h]

MPU_RASR_A1 is shown in Figure 3-133 and described in Table 3-165.

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MPU Alias 1 Region Attribute and Size
Alias for MPU_RASR

Figure 3-133 MPU_RASR_A1 Register
313029282726252423222120191817161514131211109876543210
MPU_RASR_A1
R/W-0h
Table 3-165 MPU_RASR_A1 Register Field Descriptions
BitFieldTypeResetDescription
31-0MPU_RASR_A1R/W0hAlias for MPU_RASR

3.7.4.64 MPU_RBAR_A2 Register (Offset = DACh) [Reset = 00000000h]

MPU_RBAR_A2 is shown in Figure 3-134 and described in Table 3-166.

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MPU Alias 2 Region Base Address
Alias for MPU_RBAR

Figure 3-134 MPU_RBAR_A2 Register
313029282726252423222120191817161514131211109876543210
MPU_RBAR_A2
R/W-0h
Table 3-166 MPU_RBAR_A2 Register Field Descriptions
BitFieldTypeResetDescription
31-0MPU_RBAR_A2R/W0hAlias for MPU_RBAR

3.7.4.65 MPU_RASR_A2 Register (Offset = DB0h) [Reset = 00000000h]

MPU_RASR_A2 is shown in Figure 3-135 and described in Table 3-167.

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MPU Alias 2 Region Attribute and Size
Alias for MPU_RASR

Figure 3-135 MPU_RASR_A2 Register
313029282726252423222120191817161514131211109876543210
MPU_RASR_A2
R/W-0h
Table 3-167 MPU_RASR_A2 Register Field Descriptions
BitFieldTypeResetDescription
31-0MPU_RASR_A2R/W0hAlias for MPU_RASR

3.7.4.66 MPU_RBAR_A3 Register (Offset = DB4h) [Reset = 00000000h]

MPU_RBAR_A3 is shown in Figure 3-136 and described in Table 3-168.

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MPU Alias 3 Region Base Address
Alias for MPU_RBAR

Figure 3-136 MPU_RBAR_A3 Register
313029282726252423222120191817161514131211109876543210
MPU_RBAR_A3
R/W-0h
Table 3-168 MPU_RBAR_A3 Register Field Descriptions
BitFieldTypeResetDescription
31-0MPU_RBAR_A3R/W0hAlias for MPU_RBAR

3.7.4.67 MPU_RASR_A3 Register (Offset = DB8h) [Reset = 00000000h]

MPU_RASR_A3 is shown in Figure 3-137 and described in Table 3-169.

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MPU Alias 3 Region Attribute and Size
Alias for MPU_RASR

Figure 3-137 MPU_RASR_A3 Register
313029282726252423222120191817161514131211109876543210
MPU_RASR_A3
R/W-0h
Table 3-169 MPU_RASR_A3 Register Field Descriptions
BitFieldTypeResetDescription
31-0MPU_RASR_A3R/W0hAlias for MPU_RASR

3.7.4.68 DHCSR Register (Offset = DF0h) [Reset = 00000000h]

DHCSR is shown in Figure 3-138 and described in Table 3-170.

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Debug Halting Control and Status
The purpose of this register is to provide status information about the state of the processor, enable core debug, halt and step the processor. For writes, 0xA05F must be written to higher half-word of this register, otherwise the write operation is ignored and no bits are written into the register. If not enabled for Halting mode, C_DEBUGEN = 1, all other fields are disabled. This register is not reset on a core reset. It is reset by a power-on reset. However, C_HALT always clears on a core reset. To halt on a reset, the following bits must be enabled: DEMCR.VC_CORERESET and C_DEBUGEN. Note that writes to this register in any size other than word are unpredictable. It is acceptable to read in any size, and it can be used to avoid or intentionally change a sticky bit.
Behavior of the system when writing to this register while CPU is halted (i.e. C_DEBUGEN = 1 and S_HALT= 1):
C_HALT=0, C_STEP=0, C_MASKINTS=0 Exit Debug state and start instruction execution. Exceptions activate according to the exception configuration rules.
C_HALT=0, C_STEP=0, C_MASKINTS=1 Exit Debug state and start instruction execution. PendSV, SysTick and external configurable interrupts are disabled, otherwise exceptions activate according to standard configuration rules.
C_HALT=0, C_STEP=1, C_MASKINTS=0 Exit Debug state, step an instruction and halt. Exceptions activate according to the exception configuration rules.
C_HALT=0, C_STEP=1, C_MASKINTS=1 Exit Debug state, step an instruction and halt. PendSV, SysTick and external configurable interrupts are disabled, otherwise exceptions activate according to standard configuration rules.
C_HALT=1, C_STEP=x, C_MASKINTS=x Remain in Debug state

Figure 3-138 DHCSR Register
3130292827262524
RESERVEDS_RESET_STS_RETIRE_ST
R/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDS_LOCKUPS_SLEEPS_HALTS_REGRDY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-X
15141312111098
RESERVED
R-0h
76543210
RESERVEDC_SNAPSTALLRESERVEDC_MASKINTSC_STEPC_HALTC_DEBUGEN
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-170 DHCSR Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/W0hSoftware should not rely on the value of a reserved.
When writing to this register, 0x28 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.
25S_RESET_STR/W0hIndicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still).
When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.
24S_RETIRE_STR/W0hIndicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch.
When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.
23-20RESERVEDR/W0hSoftware should not rely on the value of a reserved.
When writing to this register, 0x5 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.
19S_LOCKUPR/W0hReads as one if the core is running (not halted) and a lockup condition is present.
When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.
18S_SLEEPR/W0hIndicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must use C_HALT to gain control or wait for interrupt to wake-up.
When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.
17S_HALTR/W0hThe core is in debug state when this bit is set.
When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.
16S_REGRDYR/WXRegister Read/Write on the Debug Core Register Selector register is available. Last transfer is complete.
When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register.
15-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5C_SNAPSTALLR/W0hIf the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE_ST can detect core stalls on load/store operations.
4RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3C_MASKINTSR/W0hMask interrupts when stepping or running in halted debug. This masking does not affect NMI, fault exceptions and SVC caused by execution of the instructions. This bit must only be modified when the processor is halted (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate). Modifying C_MASKINTS while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior.
2C_STEPR/W0hSteps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1).
Modifying C_STEP while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior.
1C_HALTR/W0hHalts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset.
0C_DEBUGENR/W0hEnables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself.
The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will be unknown to software when C_DEBUGEN = 0.

3.7.4.69 DCRSR Register (Offset = DF4h) [Reset = 00000000h]

DCRSR is shown in Figure 3-139 and described in Table 3-171.

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Deubg Core Register Selector
The purpose of this register is to select the processor register to transfer data to or from. This write-only register generates a handshake to the core to transfer data to or from Debug Core Register Data Register and the selected register. Until this core transaction is complete, DHCSR.S_REGRDY is 0. Note that writes to this register in any size but word are Unpredictable.
Note that PSR registers are fully accessible this way, whereas some read as 0 when using MRS instructions. Note that all bits can be written, but some combinations cause a fault when execution is resumed.

Figure 3-139 DCRSR Register
3130292827262524
RESERVED
W-X
2322212019181716
RESERVEDREGWNR
W-XW-X
15141312111098
RESERVED
W-X
76543210
RESERVEDREGSEL
W-XW-X
Table 3-171 DCRSR Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDWXSoftware should not rely on the value of a reserved. Write 0.
16REGWNRWX1: Write
0: Read
15-5RESERVEDWXSoftware should not rely on the value of a reserved. Write 0.
4-0REGSELWXRegister select
0x00: R0
0x01: R1
0x02: R2
0x03: R3
0x04: R4
0x05: R5
0x06: R6
0x07: R7
0x08: R8
0x09: R9
0x0A: R10
0x0B: R11
0x0C: R12
0x0D: Current SP
0x0E: LR
0x0F: DebugReturnAddress
0x10: XPSR/flags, execution state information, and exception number
0x11: MSP (Main SP)
0x12: PSP (Process SP)
0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK

3.7.4.70 DCRDR Register (Offset = DF8h) [Reset = 00000000h]

DCRDR is shown in Figure 3-140 and described in Table 3-172.

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Debug Core Register Data

Figure 3-140 DCRDR Register
313029282726252423222120191817161514131211109876543210
DCRDR
R/W-X
Table 3-172 DCRDR Register Field Descriptions
BitFieldTypeResetDescription
31-0DCRDRR/WXThis register holds data for reading and writing registers to and from the processor. This is the data value written to the register selected by DCRSR. When the processor receives a request from DCRSR, this register is read or written by the processor using a normal load-store unit operation. If core register transfers are not being performed, software-based debug monitors can use this register for communication in non-halting debug. This enables flags and bits to acknowledge state and indicate if commands have been accepted to, replied to, or accepted and replied to.

3.7.4.71 DEMCR Register (Offset = DFCh) [Reset = 00000000h]

DEMCR is shown in Figure 3-141 and described in Table 3-173.

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Debug Exception and Monitor Control
The purpose of this register is vector catching and debug monitor control. This register manages exception behavior under debug. Vector catching is only available to halting debug. The upper halfword is for monitor controls and the lower halfword is for halting exception support. This register is not reset on a system reset. This register is reset by a power-on reset. The fields MON_EN, MON_PEND, MON_STEP and MON_REQ are always cleared on a core reset. The debug monitor is enabled by software in the reset handler or later, or by the **AHB-AP** port. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during a vector read or stack push error the halt occurs on the corresponding fault handler for the vector error or stack push. 2. If a late arriving interrupt detected during a vector read or stack push error it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case.

Figure 3-141 DEMCR Register
3130292827262524
RESERVEDTRCENA
R/W-0hR/W-0h
2322212019181716
RESERVEDMON_REQMON_STEPMON_PENDMON_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDVC_HARDERRVC_INTERRVC_BUSERR
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
VC_STATERRVC_CHKERRVC_NOCPERRVC_MMERRRESERVEDVC_CORERESET
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-173 DEMCR Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
24TRCENAR/W0hThis bit must be set to 1 to enable use of the trace and debug blocks: DWT, ITM, ETM and TPIU. This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger.
23-20RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
19MON_REQR/W0hThis enables the monitor to identify how it wakes up. This bit clears on a Core Reset.
0x0: Woken up by debug exception.
0x1: Woken up by MON_PEND
18MON_STEPR/W0hWhen MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored.
This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI.
17MON_PENDR/W0hPend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a power-on reset. Software in the reset handler or later, or by the DAP must enable the debug monitor.
16MON_ENR/W0hEnable the debug monitor.
When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during vectoring, vector read or stack push error, the halt occurs on the corresponding fault handler, for the vector error or stack push. 2. If a late arriving interrupt comes in during vectoring, it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case.
15-11RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
10VC_HARDERRR/W0hDebug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared.
9VC_INTERRR/W0hDebug trap on a fault occurring during an exception entry or return sequence. Ignored when DHCSR.C_DEBUGEN is cleared.
8VC_BUSERRR/W0hDebug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared.
7VC_STATERRR/W0hDebug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is cleared.
6VC_CHKERRR/W0hDebug trap on Usage Fault enabled checking errors. Ignored when DHCSR.C_DEBUGEN is cleared.
5VC_NOCPERRR/W0hDebug trap on a UsageFault access to a Coprocessor. Ignored when DHCSR.C_DEBUGEN is cleared.
4VC_MMERRR/W0hDebug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is cleared.
3-1RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0VC_CORERESETR/W0hReset Vector Catch. Halt running system if Core reset occurs. Ignored when DHCSR.C_DEBUGEN is cleared.

3.7.4.72 STIR Register (Offset = F00h) [Reset = 00000000h]

STIR is shown in Figure 3-142 and described in Table 3-174.

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Software Trigger Interrupt

Figure 3-142 STIR Register
313029282726252423222120191817161514131211109876543210
RESERVEDINTID
W-0hW-X
Table 3-174 STIR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDW0hSoftware should not rely on the value of a reserved. Write 0.
8-0INTIDWXInterrupt ID field. Writing a value to this bit-field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1.