SWCU191 February   2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA

 

  1. 1 Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  2. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Analog Peripherals
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  3. 3 Arm® Cortex®-M4 Processor
    1. 3.1 Arm® Cortex®-M4 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Arm® Cortex®-M4 System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4 Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4 Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Arm® Cortex®-M4 Processor Registers
      1. 3.7.1 CPU_DWT Registers
      2. 3.7.2 CPU_FPB Registers
      3. 3.7.3 CPU_ITM Registers
      4. 3.7.4 CPU_SCS Registers
      5. 3.7.5 CPU_TPIU Registers
  4. 4 Memory Map
    1. 4.1 Memory Map
  5. 5 Arm® Cortex®-M4 Peripherals
    1. 5.1 Arm® Cortex®-M4 Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  6. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  7. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  8. 8 Power, Reset and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 OSC_DIG Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  9. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  10. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM Registers
  11. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  13. 13Cryptography
    1. 13.1 AES Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master Transfer Protection
          1. 13.5.4.2.1 Master Transfer Protection Control
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Encryption and Decryption
        1. 13.7.3.1 Key Store
          1. 13.7.3.1.1 Load Keys From External Memory
        2. 13.7.3.2 Basic AES Modes
          1. 13.7.3.2.1 AES-ECB
          2. 13.7.3.2.2 AES-CBC
          3. 13.7.3.2.3 AES-CTR
          4. 13.7.3.2.4 Programming Sequence With DMA Data
        3. 13.7.3.3 CBC-MAC
          1. 13.7.3.3.1 Programming Sequence for CBC-MAC
        4. 13.7.3.4 AES-CCM
          1. 13.7.3.4.1 Programming Sequence for AES-CCM
      4. 13.7.4 Exceptions Handling
        1. 13.7.4.1 Soft Reset
        2. 13.7.4.2 External Port Errors
        3. 13.7.4.3 Key Store Errors
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  14. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  15. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 μDMA Registers
  16. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  17. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  18. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  19. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  20. 20AUX Domain Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
      3. 20.2.3 SCE Clock Emulation
    3. 20.3 Digital Peripheral Modules
      1. 20.3.1 Overview
        1. 20.3.1.1 DDI Control-Configuration
      2. 20.3.2 AIODIO
        1. 20.3.2.1 Introduction
        2. 20.3.2.2 Functional Description
          1. 20.3.2.2.1 Mapping to DIO Pins
          2. 20.3.2.2.2 Configuration
          3. 20.3.2.2.3 GPIO Mode
          4. 20.3.2.2.4 Input Buffer
          5. 20.3.2.2.5 Data Output Source
      3. 20.3.3 SMPH
        1. 20.3.3.1 Introduction
        2. 20.3.3.2 Functional Description
        3. 20.3.3.3 Semaphore Allocation in TI Software
      4. 20.3.4 Time-to-Digital Converter (TDC)
        1. 20.3.4.1 Introduction
        2. 20.3.4.2 Functional Description
          1. 20.3.4.2.1 Command
          2. 20.3.4.2.2 Conversion Time Configuration
          3. 20.3.4.2.3 Status and Result
          4. 20.3.4.2.4 Clock Source Selection
            1. 20.3.4.2.4.1 Counter Clock
            2. 20.3.4.2.4.2 Reference Clock
          5. 20.3.4.2.5 Start and Stop Events
          6. 20.3.4.2.6 Prescaler
        3. 20.3.4.3 Supported Measurement Types
          1. 20.3.4.3.1 Measure Pulse Width
          2. 20.3.4.3.2 Measure Frequency
          3. 20.3.4.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.3.4.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.3.4.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.3.4.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.3.4.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.3.4.3.4 Pulse Counting
      5. 20.3.5 Timer01
        1. 20.3.5.1 Introduction
        2. 20.3.5.2 Functional Description
    4. 20.4 Analog Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 ADI Control-Configuration
        2. 20.4.1.2 Block Diagram
      2. 20.4.2 Analog-to-Digital Converter (ADC)
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Input Selection and Scaling
          2. 20.4.2.2.2 Reference Selection
          3. 20.4.2.2.3 ADC Sample Mode
          4. 20.4.2.2.4 ADC Clock Source
          5. 20.4.2.2.5 ADC Trigger
          6. 20.4.2.2.6 Sample FIFO
          7. 20.4.2.2.7 µDMA Interface
          8. 20.4.2.2.8 Resource Ownership and Usage
      3. 20.4.3 COMPA
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
          1. 20.4.3.2.1 Input Selection
          2. 20.4.3.2.2 Reference Selection
          3. 20.4.3.2.3 LPM Bias and COMPA Enable
          4. 20.4.3.2.4 Resource Ownership and Usage
      4. 20.4.4 COMPB
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 Input Selection
          2. 20.4.4.2.2 Reference Selection
          3. 20.4.4.2.3 Resource Ownership and Usage
            1. 20.4.4.2.3.1 System CPU Wakeup
      5. 20.4.5 Reference DAC
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Reference Selection
          2. 20.4.5.2.2 Output Voltage Control and Range
          3. 20.4.5.2.3 Sample Clock
            1. 20.4.5.2.3.1 Automatic Phase Control
            2. 20.4.5.2.3.2 Manual Phase Control
            3. 20.4.5.2.3.3 Operational Mode Dependency
          4. 20.4.5.2.4 Output Selection
            1. 20.4.5.2.4.1 Buffer
            2. 20.4.5.2.4.2 External Load
            3. 20.4.5.2.4.3 COMPA_REF
            4. 20.4.5.2.4.4 COMPB_REF
          5. 20.4.5.2.5 LPM Bias
          6. 20.4.5.2.6 Resource Ownership and Usage
      6. 20.4.6 ISRC
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
          1. 20.4.6.2.1 Programmable Current
          2. 20.4.6.2.2 Voltage Reference
          3. 20.4.6.2.3 ISRC Enable
          4. 20.4.6.2.4 Temperature Dependency
          5. 20.4.6.2.5 Resource Ownership and Usage
    5. 20.5 Event Routing and Usage
      1. 20.5.1 AUX Event Bus
        1. 20.5.1.1 Event Signals
        2. 20.5.1.2 Event Subscribers
          1. 20.5.1.2.1 Event Detection
            1. 20.5.1.2.1.1 Detection of Asynchronous Events
            2. 20.5.1.2.1.2 Detection of Synchronous Events
      2. 20.5.2 Event Observation on External Pin
      3. 20.5.3 Events From MCU Domain
      4. 20.5.4 Events to MCU Domain
      5. 20.5.5 Events From AON Domain
      6. 20.5.6 Events to AON Domain
      7. 20.5.7 µDMA Interface
    6. 20.6 AUX Domain Peripheral Registers
      1. 20.6.1 ADI_4_AUX Registers
      2. 20.6.2 AUX_AIODIO Registers
      3. 20.6.3 AUX_EVCTL Registers
      4. 20.6.4 AUX_SMPH Registers
      5. 20.6.5 AUX_TDC Registers
      6. 20.6.6 AUX_TIMER01 Registers
      7. 20.6.7 AUX_ANAIF Registers
      8. 20.6.8 AUX_SYSIF Registers
  21. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  22. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  23. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  24. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  25. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  26. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
        1.       Revision History

13.9.1 CRYPTO Registers

Table 13-18 lists the memory-mapped registers for the CRYPTO registers. All register offset addresses not listed in Table 13-18 should be considered as reserved locations and the register contents should not be modified.

Table 13-18 CRYPTO Registers
OffsetAcronymRegister NameSection
0hDMACH0CTLDMA Channel 0 Control#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMACH0CTL
4hDMACH0EXTADDRDMA Channel 0 External Address#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMACH0EXTADDR
ChDMACH0LENDMA Channel 0 Length#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMACH0LEN
18hDMASTATDMA Controller Status#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMASTAT
1ChDMASWRESETDMA Controller Software Reset#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMASWRESET
20hDMACH1CTLDMA Channel 1 Control#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMACH1CTL
24hDMACH1EXTADDRDMA Channel 1 External Address#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMACH1EXTADDR
2ChDMACH1LENDMA Channel 1 Length#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMACH1LEN
78hDMABUSCFGDMA Controller Master Configuration#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMABUSCFG
7ChDMAPORTERRDMA Controller Port Error#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMAPORTERR
FChDMAHWVERDMA Controller Version#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMAHWVER
400hKEYWRITEAREAKey Write Area#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_KEYWRITEAREA
404hKEYWRITTENAREAKey Written Area Status#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_KEYWRITTENAREA
408hKEYSIZEKey Size#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_KEYSIZE
40ChKEYREADAREAKey Read Area#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_KEYREADAREA
500h + formulaAESKEY2_yClear AES_KEY2/GHASH Key#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESKEY2
510h + formulaAESKEY3_yClear AES_KEY3#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESKEY3
540h + formulaAESIV_yAES Initialization Vector#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESIV
550hAESCTLAES Input/Output Buffer Control#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESCTL
554hAESDATALEN0Crypto Data Length LSW#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESDATALEN0
558hAESDATALEN1Crypto Data Length MSW#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESDATALEN1
55ChAESAUTHLENAES Authentication Length#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESAUTHLEN
560hAESDATAOUT0Data Input/Output#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESDATAOUT0
560hAESDATAIN0AES Data Input/Output 0#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESDATAIN0
564hAESDATAOUT1AES Data Input/Output 3#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESDATAOUT1
564hAESDATAIN1AES Data Input/Output 1#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESDATAIN1
568hAESDATAOUT2AES Data Input/Output 2#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESDATAOUT2
568hAESDATAIN2AES Data Input/Output 2#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESDATAIN2
56ChAESDATAOUT3AES Data Input/Output 3#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESDATAOUT3
56ChAESDATAIN3Data Input/Output#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESDATAIN3
570h + formulaAESTAGOUT_yAES Tag Output#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_AESTAGOUT
700hALGSELMaster Algorithm Select#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_ALGSEL
704hDMAPROTCTLMaster Protection Control#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_DMAPROTCTL
740hSWRESETSoftware Reset#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_SWRESET
780hIRQTYPEControl Interrupt Configuration#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_IRQTYPE
784hIRQENInterrupt Enable#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_IRQEN
788hIRQCLRInterrupt Clear#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_IRQCLR
78ChIRQSETInterrupt Set#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_IRQSET
790hIRQSTATInterrupt Status#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_IRQSTAT
7FChHWVERCTRL Module Version#CRYPTO_WRAPPER_CRYPTO_WRAPPER_MAP1_CRYPTO_WRAPPER_ALL_HWVER

Complex bit access types are encoded to fit into small table cells. Table 13-19 shows the codes that are used for access types in this section.

Table 13-19 CRYPTO Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W0CW
0C		Write
0 to clear
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

13.9.1.1 DMACH0CTL Register (Offset = 0h) [Reset = 00000000h]

DMACH0CTL is shown in Figure 13-3 and described in Table 13-20.

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DMA Channel 0 Control

Figure 13-3 DMACH0CTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPRIOEN
R-0hR/W-0hR/W-0h
Table 13-20 DMACH0CTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1PRIOR/W0hChannel priority:
A channel with high priority will be served before a channel with low priority in cases with simultaneous access requests. If both channels have the same priority access of the channels to the external port is arbitrated using a Round Robin scheme.
0h = Priority low
1h = Priority high
0ENR/W0hDMA Channel 0 Control
0h = Channel disabled
1h = Channel enabled

13.9.1.2 DMACH0EXTADDR Register (Offset = 4h) [Reset = 00000000h]

DMACH0EXTADDR is shown in Figure 13-4 and described in Table 13-21.

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DMA Channel 0 External Address

Figure 13-4 DMACH0EXTADDR Register
313029282726252423222120191817161514131211109876543210
ADDR
R/W-0h
Table 13-21 DMACH0EXTADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hChannel external address value.
Holds the last updated external address after being sent to the master interface.

13.9.1.3 DMACH0LEN Register (Offset = Ch) [Reset = 00000000h]

DMACH0LEN is shown in Figure 13-5 and described in Table 13-22.

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DMA Channel 0 Length

Figure 13-5 DMACH0LEN Register
313029282726252423222120191817161514131211109876543210
RESERVEDLEN
R-0hR/W-0h
Table 13-22 DMACH0LEN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0LENR/W0hDMA transfer length in bytes.
During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface.
Note: Writing a non-zero value to this register field starts the transfer if the channel is enabled by setting DMACH0CTL.EN.

13.9.1.4 DMASTAT Register (Offset = 18h) [Reset = 00000000h]

DMASTAT is shown in Figure 13-6 and described in Table 13-23.

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DMA Controller Status

Figure 13-6 DMASTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDPORT_ERRRESERVED
R-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCH1_ACTIVECH0_ACTIVE
R-0hR-0hR-0h
Table 13-23 DMASTAT Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17PORT_ERRR0hReflects possible transfer errors on the AHB port.
16-2RESERVEDR0hReserved
1CH1_ACTIVER0hThis register field indicates if DMA channel 1 is active or not.
0: Not active
1: Active
0CH0_ACTIVER0hThis register field indicates if DMA channel 0 is active or not.
0: Not active
1: Active

13.9.1.5 DMASWRESET Register (Offset = 1Ch) [Reset = 00000000h]

DMASWRESET is shown in Figure 13-7 and described in Table 13-24.

Return to the Summary Table.

DMA Controller Software Reset

Figure 13-7 DMASWRESET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESET
R-0hW0C-0h
Table 13-24 DMASWRESET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0RESETW0C0hSoftware reset enable
0: Disable
1: Enable (self-cleared to zero).
Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE and DMASTAT.CH1_ACTIVE.

13.9.1.6 DMACH1CTL Register (Offset = 20h) [Reset = 00000000h]

DMACH1CTL is shown in Figure 13-8 and described in Table 13-25.

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DMA Channel 1 Control

Figure 13-8 DMACH1CTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPRIOEN
R-0hR/W-0hR/W-0h
Table 13-25 DMACH1CTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1PRIOR/W0hChannel priority:
A channel with high priority will be served before a channel with low priority in cases with simultaneous access requests. If both channels have the same priority access of the channels to the external port is arbitrated using a Round Robin scheme.
0h = Priority low
1h = Priority high
0ENR/W0hChannel enable:
Note: Disabling an active channel will interrupt the DMA operation. The ongoing block transfer will be completed, but no new transfers will be requested.
0h = Channel disabled
1h = Channel enabled

13.9.1.7 DMACH1EXTADDR Register (Offset = 24h) [Reset = 00000000h]

DMACH1EXTADDR is shown in Figure 13-9 and described in Table 13-26.

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DMA Channel 1 External Address

Figure 13-9 DMACH1EXTADDR Register
313029282726252423222120191817161514131211109876543210
ADDR
R/W-0h
Table 13-26 DMACH1EXTADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hChannel external address value.
Holds the last updated external address after being sent to the master interface.

13.9.1.8 DMACH1LEN Register (Offset = 2Ch) [Reset = 00000000h]

DMACH1LEN is shown in Figure 13-10 and described in Table 13-27.

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DMA Channel 1 Length

Figure 13-10 DMACH1LEN Register
313029282726252423222120191817161514131211109876543210
RESERVEDLEN
R-0hR/W-0h
Table 13-27 DMACH1LEN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0LENR/W0hDMA transfer length in bytes.
During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface.
Note: Writing a non-zero value to this register field starts the transfer if the channel is enabled by setting DMACH1CTL.EN.

13.9.1.9 DMABUSCFG Register (Offset = 78h) [Reset = 00002400h]

DMABUSCFG is shown in Figure 13-11 and described in Table 13-28.

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DMA Controller Master Configuration

Figure 13-11 DMABUSCFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AHB_MST1_BURST_SIZEAHB_MST1_IDLE_ENAHB_MST1_INCR_ENAHB_MST1_LOCK_ENAHB_MST1_BIGEND
R/W-2hR/W-0hR/W-1hR/W-0hR/W-0h
76543210
RESERVED
R-0h
Table 13-28 DMABUSCFG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-12AHB_MST1_BURST_SIZER/W2hMaximum burst size that can be performed on the AHB bus
2h = 4_BYTE : 4 bytes
3h = 8_BYTE : 8 bytes
4h = 16_BYTE : 16 bytes
5h = 32_BYTE : 32 bytes
6h = 64_BYTE : 64 bytes
11AHB_MST1_IDLE_ENR/W0hIdle transfer insertion between consecutive burst transfers on AHB
0h = Do not insert idle transfers.
1h = Idle transfer insertion enabled
10AHB_MST1_INCR_ENR/W1hBurst length type of AHB transfer
0h = Unspecified length burst transfers
1h = Fixed length bursts or single transfers
9AHB_MST1_LOCK_ENR/W0hLocked transform on AHB
0h = Transfers are not locked
1h = Transfers are locked
8AHB_MST1_BIGENDR/W0hEndianess for the AHB master
0h = Little Endian
1h = Big Endian
7-0RESERVEDR0hReserved

13.9.1.10 DMAPORTERR Register (Offset = 7Ch) [Reset = 00000000h]

DMAPORTERR is shown in Figure 13-12 and described in Table 13-29.

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DMA Controller Port Error

Figure 13-12 DMAPORTERR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAHB_ERRRESERVEDLAST_CHRESERVED
R-0hR-0hR-0hR-0hR-0h
76543210
RESERVED
R-0h
Table 13-29 DMAPORTERR Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12AHB_ERRR0hA 1 indicates that the Crypto peripheral has detected an AHB bus error
11-10RESERVEDR0hReserved
9LAST_CHR0hIndicates which channel was serviced last (channel 0 or channel 1) by the AHB master port.
8-0RESERVEDR0hReserved

13.9.1.11 DMAHWVER Register (Offset = FCh) [Reset = 01012ED1h]

DMAHWVER is shown in Figure 13-13 and described in Table 13-30.

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DMA Controller Version

Figure 13-13 DMAHWVER Register
31302928272625242322212019181716
RESERVEDHW_MAJOR_VERHW_MINOR_VERHW_PATCH_LVL
R-0hR-1hR-0hR-1h
1514131211109876543210
VER_NUM_COMPLVER_NUM
R-2EhR-D1h
Table 13-30 DMAHWVER Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-24HW_MAJOR_VERR1hMajor version number
23-20HW_MINOR_VERR0hMinor version number
19-16HW_PATCH_LVLR1hPatch level.
15-8VER_NUM_COMPLR2EhBit-by-bit complement of the VER_NUM field bits.
7-0VER_NUMRD1hVersion number of the DMA Controller (209)

13.9.1.12 KEYWRITEAREA Register (Offset = 400h) [Reset = 00000000h]

KEYWRITEAREA is shown in Figure 13-14 and described in Table 13-31.

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Key Write Area

Figure 13-14 KEYWRITEAREA Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RAM_AREA7RAM_AREA6RAM_AREA5RAM_AREA4RAM_AREA3RAM_AREA2RAM_AREA1RAM_AREA0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 13-31 KEYWRITEAREA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7RAM_AREA7R/W0hRepresents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written.
Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
6RAM_AREA6R/W0hRepresents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written.
Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
5RAM_AREA5R/W0hRepresents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written.
Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
4RAM_AREA4R/W0hRepresents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written.
Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
3RAM_AREA3R/W0hRepresents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written.
Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
2RAM_AREA2R/W0hRepresents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written.
Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
1RAM_AREA1R/W0hRepresents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written.
Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
0RAM_AREA0R/W0hRepresents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written.
Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written

13.9.1.13 KEYWRITTENAREA Register (Offset = 404h) [Reset = 00000000h]

KEYWRITTENAREA is shown in Figure 13-15 and described in Table 13-32.

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Key Written Area Status
This register shows which areas of the key store RAM contain valid written keys.
When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory.
Attempting to write to a key area that already contains a valid key is not allowed and will result in an error.

Figure 13-15 KEYWRITTENAREA Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RAM_AREA_WRITTEN7RAM_AREA_WRITTEN6RAM_AREA_WRITTEN5RAM_AREA_WRITTEN4RAM_AREA_WRITTEN3RAM_AREA_WRITTEN2RAM_AREA_WRITTEN1RAM_AREA_WRITTEN0
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 13-32 KEYWRITTENAREA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7RAM_AREA_WRITTEN7R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
6RAM_AREA_WRITTEN6R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
5RAM_AREA_WRITTEN5R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
4RAM_AREA_WRITTEN4R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
3RAM_AREA_WRITTEN3R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
2RAM_AREA_WRITTEN2R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
1RAM_AREA_WRITTEN1R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
0RAM_AREA_WRITTEN0R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information

13.9.1.14 KEYSIZE Register (Offset = 408h) [Reset = 00000001h]

KEYSIZE is shown in Figure 13-16 and described in Table 13-33.

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Key Size
This register defines the size of the keys that are written with DMA.

Figure 13-16 KEYSIZE Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSIZE
R-0hR/W-1h
Table 13-33 KEYSIZE Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0SIZER/W1hKey size
When writing to this register, KEYWRITTENAREA will be reset.
Note: For the Crypto peripheral this field is fixed to 128 bits. For software compatibility KEYWRITTENAREA will be reset when writing to this register.
1h = 128_BIT : 128 bits

13.9.1.15 KEYREADAREA Register (Offset = 40Ch) [Reset = 00000008h]

KEYREADAREA is shown in Figure 13-17 and described in Table 13-34.

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Key Read Area

Figure 13-17 KEYREADAREA Register
3130292827262524
BUSYRESERVED
R-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRAM_AREA
R-0hR/W-8h
Table 13-34 KEYREADAREA Register Field Descriptions
BitFieldTypeResetDescription
31BUSYR0hKey store operation busy status flag (read only)
0: operation is completed.
1: operation is not completed and the key store is busy.
30-4RESERVEDR0hReserved
3-0RAM_AREAR/W8hSelects the area of the key store RAM from where the key needs to be read that will be written to the AES engine.
Only RAM areas that contain valid written keys can be selected.
0h = RAM Area 0
1h = RAM Area 1
2h = RAM Area 2
3h = RAM Area 3
4h = RAM Area 4
5h = RAM Area 5
6h = RAM Area 6
7h = RAM Area 7
8h = No RAM

13.9.1.16 AESKEY2_y Register (Offset = 500h + formula) [Reset = 00000000h]

AESKEY2_y is shown in Figure 13-18 and described in Table 13-35.

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Clear AES_KEY2/GHASH Key

Offset = 500h + (y * 4h); where y = 0h to 3h

Figure 13-18 AESKEY2_y Register
313029282726252423222120191817161514131211109876543210
KEY2
W-0h
Table 13-35 AESKEY2_y Register Field Descriptions
BitFieldTypeResetDescription
31-0KEY2W0hAESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register array.
The interpretation of this field depends on the crypto operation mode.

13.9.1.17 AESKEY3_y Register (Offset = 510h + formula) [Reset = 00000000h]

AESKEY3_y is shown in Figure 13-19 and described in Table 13-36.

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Clear AES_KEY3

Offset = 510h + (y * 4h); where y = 0h to 3h

Figure 13-19 AESKEY3_y Register
313029282726252423222120191817161514131211109876543210
KEY3
W-0h
Table 13-36 AESKEY3_y Register Field Descriptions
BitFieldTypeResetDescription
31-0KEY3W0hAESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register arrary.
The interpretation of this field depends on the crypto operation mode.

13.9.1.18 AESIV_y Register (Offset = 540h + formula) [Reset = 00000000h]

AESIV_y is shown in Figure 13-20 and described in Table 13-37.

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AES Initialization Vector

Offset = 540h + (y * 4h); where y = 0h to 3h

Figure 13-20 AESIV_y Register
313029282726252423222120191817161514131211109876543210
IV
R/W-0h
Table 13-37 AESIV_y Register Field Descriptions
BitFieldTypeResetDescription
31-0IVR/W0hThe interpretation of this field depends on the crypto operation mode.

13.9.1.19 AESCTL Register (Offset = 550h) [Reset = 80000000h]

AESCTL is shown in Figure 13-21 and described in Table 13-38.

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AES Input/Output Buffer Control

Figure 13-21 AESCTL Register
3130292827262524
CONTEXT_RDYSAVED_CONTEXT_RDYSAVE_CONTEXTRESERVEDCCM_M
R-1hR/W-0hR/W-0hR-0hR/W-0h
2322212019181716
CCM_MCCM_LCCMRESERVED
R/W-0hR/W-0hR/W-0hR-0h
15141312111098
CBC_MACRESERVEDCTR_WIDTH
R/W-0hR-0hR/W-0h
76543210
CTR_WIDTHCTRCBCKEY_SIZEDIRINPUT_RDYOUTPUT_RDY
R/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 13-38 AESCTL Register Field Descriptions
BitFieldTypeResetDescription
31CONTEXT_RDYR1hIf 1, this status bit indicates that the context data registers can be overwritten and the Host is permitted to write the next context. Writing a context means writing either a mode, the crypto length or AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers
30SAVED_CONTEXT_RDYR/W0hIf read as 1, this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the Host to retrieve. This bit is only asserted if SAVE_CONTEXT is set to 1. The bit is mutually exclusive with CONTEXT_RDY.
Writing 1 clears the bit to zero, indicating the Crypto peripheral can start its next operation. This bit is also cleared when the 4th word of the output TAG and/or IV is read.
Note: All other mode bit writes will be ignored when this mode bit is written with 1.
Note: This bit is controlled automatically by the Crypto peripheral for TAG read DMA operations.
For typical use, this bit does NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral.
29SAVE_CONTEXTR/W0hIV must be read before the AES engine can start a new operation.
28-25RESERVEDR0hReserved
24-22CCM_MR/W0hDefines M that indicates the length of the authentication field for CCM operations
the authentication field length equals two times the value of CCM_M plus one.
Note: The Crypto peripheral always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported.
21-19CCM_LR/W0hDefines L that indicates the width of the length field for CCM operations
the length field in bytes equals the value of CMM_L plus one. All values are supported.
18CCMR/W0hAES-CCM mode enable.
AES-CCM is a combined mode, using AES for both authentication and encryption.
Note: Selecting AES-CCM mode requires writing of AESDATALEN1.LEN_MSW and AESDATALEN0.LEN_LSW after all other registers.
Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR
selecting other AES modes than CTR mode is invalid.
17-16RESERVEDR0hReserved
15CBC_MACR/W0hMAC mode enable.
The DIR bit must be set to 1 for this mode.
Selecting this mode requires writing the AESDATALEN1.LEN_MSW and AESDATALEN0.LEN_LSW registers after all other registers.
14-9RESERVEDR0hReserved
8-7CTR_WIDTHR/W0hSpecifies the counter width for AES-CTR mode
0h = 32_BIT : 32 bits
1h = 64_BIT : 64 bits
2h = 96_BIT : 96 bits
3h = 128_BIT : 128 bits
6CTRR/W0hAES-CTR mode enable
This bit must also be set for CCM, when encryption/decryption is required.
5CBCR/W0hCBC mode enable
4-3KEY_SIZER0hThis field specifies the key size.
The key size is automatically configured when a new key is loaded via the key store module.
00 = N/A - reserved
01 = 128 bits
10 = N/A - reserved
11 = N/A - reserved
For the Crypto peripheral this field is fixed to 128 bits.
2DIRR/W0hDirection.
0 : Decrypt operation is performed.
1 : Encrypt operation is performed.
This bit must be written with a 1 when CBC-MAC is selected.
1INPUT_RDYR/W0hIf read as 1, this status bit indicates that the 16-byte AES input buffer is empty. The Host is permitted to write the next block of data.
Writing a 0 clears the bit to zero and indicates that the AES engine can use the provided input data block.
Writing a 1 to this bit will be ignored.
Note: For DMA operations, this bit is automatically controlled by the Crypto peripheral.
After reset, this bit is 0. After writing a context (note 1), this bit will become 1.
For typical use, this bit does NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral.
0OUTPUT_RDYR/W0hIf read as 1, this status bit indicates that an AES output block is available to be retrieved by the Host.
Writing a 0 clears the bit to zero and indicates that output data is read by the Host. The AES engine can provide a next output data block.
Writing a 1 to this bit will be ignored.
Note: For DMA operations, this bit is automatically controlled by the Crypto peripheral.
For typical use, this bit does NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral.

13.9.1.20 AESDATALEN0 Register (Offset = 554h) [Reset = 00000000h]

AESDATALEN0 is shown in Figure 13-22 and described in Table 13-39.

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Crypto Data Length LSW

Figure 13-22 AESDATALEN0 Register
313029282726252423222120191817161514131211109876543210
LEN_LSW
W-0h
Table 13-39 AESDATALEN0 Register Field Descriptions
BitFieldTypeResetDescription
31-0LEN_LSWW0hUsed to write the Length values to the Crypto peripheral.
This register contains bits [31:0] of the combined data length.

13.9.1.21 AESDATALEN1 Register (Offset = 558h) [Reset = 00000000h]

AESDATALEN1 is shown in Figure 13-23 and described in Table 13-40.

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Crypto Data Length MSW

Figure 13-23 AESDATALEN1 Register
31302928272625242322212019181716
RESERVEDLEN_MSW
R-0hW-0h
1514131211109876543210
LEN_MSW
W-0h
Table 13-40 AESDATALEN1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-0LEN_MSWW0hBits [60:32] of the combined data length.
Bits [60:0] of the crypto length registers AESDATALEN1 and AESDATALEN0 store the cryptographic data length in bytes for all modes. Once processing with this context starts, this length decrements to zero. Data lengths up to (261 - 1) bytes are allowed.
A write to this register triggers the engine to start using this context. This is valid for all modes except CCM. For the combined modes (CCM), this length does not include the authentication only data
the authentication length is specified in the AESAUTHLEN.LEN. All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero.
For the basic encryption modes (ECB/CBC/CTR) it is allowed to program zero to the length field
in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes
bit aligned data streams are not supported by the Crypto peripheral. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes.

13.9.1.22 AESAUTHLEN Register (Offset = 55Ch) [Reset = 00000000h]

AESAUTHLEN is shown in Figure 13-24 and described in Table 13-41.

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AES Authentication Length

Figure 13-24 AESAUTHLEN Register
313029282726252423222120191817161514131211109876543210
LEN
W-0h
Table 13-41 AESAUTHLEN Register Field Descriptions
BitFieldTypeResetDescription
31-0LENW0hAuthentication data length in bytes for combined mode, CCM only.
Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes. Once processing with this context is started, this length decrements to zero.
Writing this register triggers the engine to start using this context for CCM.

13.9.1.23 AESDATAOUT0 Register (Offset = 560h) [Reset = 00000000h]

AESDATAOUT0 is shown in Figure 13-25 and described in Table 13-42.

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Data Input/Output

Figure 13-25 AESDATAOUT0 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 13-42 AESDATAOUT0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hData register 0 for output block data from the Crypto peripheral.
These bits = AES Output Data[31:0] of [127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must be written.
For the modes with authentication (CBC-MAC and CCM), the invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.24 AESDATAIN0 Register (Offset = 560h) [Reset = 00000000h]

AESDATAIN0 is shown in Figure 13-26 and described in Table 13-43.

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AES Data Input/Output 0

Figure 13-26 AESDATAIN0 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 13-43 AESDATAIN0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hData registers for input block data to the Crypto peripheral.
These bits = AES Input Data[31:0] of [127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range will store the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to AESCTL.INPUT_RDY.
Note: AES typically operates on 128 bits block multiple input data. The CTR and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. For CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically pads or masks misaligned ending data blocks with zeroes for CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored.

13.9.1.25 AESDATAOUT1 Register (Offset = 564h) [Reset = 00000000h]

AESDATAOUT1 is shown in Figure 13-27 and described in Table 13-44.

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AES Data Input/Output 3

Figure 13-27 AESDATAOUT1 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 13-44 AESDATAOUT1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hData registers for output block data from the Crypto peripheral.
These bits = AES Output Data[63:32] of [127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must be written.
For the modes with authentication (CBC-MAC and CCM), the invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.26 AESDATAIN1 Register (Offset = 564h) [Reset = 00000000h]

AESDATAIN1 is shown in Figure 13-28 and described in Table 13-45.

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AES Data Input/Output 1

Figure 13-28 AESDATAIN1 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 13-45 AESDATAIN1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hData registers for input block data to the Crypto peripheral.
These bits = AES Input Data[63:32] of [127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range will store the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to AESCTL.INPUT_RDY.
Note: AES typically operates on 128 bits block multiple input data. The CTR and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. For CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically pads or masks misaligned ending data blocks with zeroes for CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored.

13.9.1.27 AESDATAOUT2 Register (Offset = 568h) [Reset = 00000000h]

AESDATAOUT2 is shown in Figure 13-29 and described in Table 13-46.

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AES Data Input/Output 2

Figure 13-29 AESDATAOUT2 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 13-46 AESDATAOUT2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hData registers for output block data from the Crypto peripheral.
These bits = AES Output Data[95:64] of [127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must be written.
For the modes with authentication (CBC-MAC and CCM), the invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.28 AESDATAIN2 Register (Offset = 568h) [Reset = 00000000h]

AESDATAIN2 is shown in Figure 13-30 and described in Table 13-47.

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AES Data Input/Output 2

Figure 13-30 AESDATAIN2 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 13-47 AESDATAIN2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hData registers for input block data to the Crypto peripheral.
These bits = AES Input Data[95:64] of [127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range will store the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to AESCTL.INPUT_RDY.
Note: AES typically operates on 128 bits block multiple input data. The CTR and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. For CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically pads or masks misaligned ending data blocks with zeroes for CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored.

13.9.1.29 AESDATAOUT3 Register (Offset = 56Ch) [Reset = 00000000h]

AESDATAOUT3 is shown in Figure 13-31 and described in Table 13-48.

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AES Data Input/Output 3

Figure 13-31 AESDATAOUT3 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 13-48 AESDATAOUT3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hData registers for output block data from the Crypto peripheral.
These bits = AES Output Data[127:96] of [127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must be written.
For the modes with authentication (CBC-MAC and CCM), the invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.30 AESDATAIN3 Register (Offset = 56Ch) [Reset = 00000000h]

AESDATAIN3 is shown in Figure 13-32 and described in Table 13-49.

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Data Input/Output

Figure 13-32 AESDATAIN3 Register
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 13-49 AESDATAIN3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hData registers for input block data to the Crypto peripheral.
These bits = AES Input Data[127:96] of [127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range will store the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to AESCTL.INPUT_RDY.
Note: AES typically operates on 128 bits block multiple input data. The CTR and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. For CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically pads or masks misaligned ending data blocks with zeroes for CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored.

13.9.1.31 AESTAGOUT_y Register (Offset = 570h + formula) [Reset = 00000000h]

AESTAGOUT_y is shown in Figure 13-33 and described in Table 13-50.

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AES Tag Output

Offset = 570h + (y * 4h); where y = 0h to 3h

Figure 13-33 AESTAGOUT_y Register
313029282726252423222120191817161514131211109876543210
TAG
R-0h
Table 13-50 AESTAGOUT_y Register Field Descriptions
BitFieldTypeResetDescription
31-0TAGR0hThis register contains the authentication TAG for the combined and authentication-only modes.

13.9.1.32 ALGSEL Register (Offset = 700h) [Reset = 00000000h]

ALGSEL is shown in Figure 13-34 and described in Table 13-51.

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Master Algorithm Select
This register configures the internal destination of the DMA controller.

Figure 13-34 ALGSEL Register
3130292827262524
TAGRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDAESKEY_STORE
R-0hR/W-0hR/W-0h
Table 13-51 ALGSEL Register Field Descriptions
BitFieldTypeResetDescription
31TAGR/W0hIf this bit is cleared to 0, the DMA operation involves only data.
If this bit is set, the DMA operation includes a TAG (Authentication Result / Digest).
30-2RESERVEDR0hReserved
1AESR/W0hIf set to 1, the AES data is loaded via DMA
Both Read and Write maximum transfer size to DMA engine is set to 16 bytes
0KEY_STORER/W0hIf set to 1, selects the Key Store to be loaded via DMA.
The maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16, 24 and 32 bytes are allowed)

13.9.1.33 DMAPROTCTL Register (Offset = 704h) [Reset = 00000000h]

DMAPROTCTL is shown in Figure 13-35 and described in Table 13-52.

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Master Protection Control

Figure 13-35 DMAPROTCTL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDEN
R-0hR/W-0h
Table 13-52 DMAPROTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hSelect AHB transfer protection control for DMA transfers using the key store area as destination.
0 : transfers use 'USER' type access.
1 : transfers use 'PRIVILEGED' type access.

13.9.1.34 SWRESET Register (Offset = 740h) [Reset = 00000000h]

SWRESET is shown in Figure 13-36 and described in Table 13-53.

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Software Reset

Figure 13-36 SWRESET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESET
R-0hR/W1C-0h
Table 13-53 SWRESET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0RESETR/W1C0hIf this bit is set to 1, the following modules are reset:
- Master control internal state is reset. That includes interrupt, error status register and result available interrupt generation FSM.
- Key store module state is reset. That includes clearing the Written Area flags
therefore the keys must be reloaded to the key store module.
Writing 0 has no effect.
The bit is self cleared after executing the reset.

13.9.1.35 IRQTYPE Register (Offset = 780h) [Reset = 00000000h]

IRQTYPE is shown in Figure 13-37 and described in Table 13-54.

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Control Interrupt Configuration

Figure 13-37 IRQTYPE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLEVEL
R-0hR/W-0h
Table 13-54 IRQTYPE Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0LEVELR/W0hIf this bit is 0, the interrupt output is a pulse.
If this bit is set to 1, the interrupt is a level interrupt that must be cleared by writing the interrupt clear register.
This bit is applicable for both interrupt output signals.

13.9.1.36 IRQEN Register (Offset = 784h) [Reset = 00000000h]

IRQEN is shown in Figure 13-38 and described in Table 13-55.

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Interrupt Enable

Figure 13-38 IRQEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA_IN_DONERESULT_AVAIL
R-0hR/W-0hR/W-0h
Table 13-55 IRQEN Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1DMA_IN_DONER/W0hThis bit enables IRQSTAT.DMA_IN_DONE as source for IRQ.
0RESULT_AVAILR/W0hThis bit enables IRQSTAT.RESULT_AVAIL as source for IRQ.

13.9.1.37 IRQCLR Register (Offset = 788h) [Reset = 00000000h]

IRQCLR is shown in Figure 13-39 and described in Table 13-56.

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Interrupt Clear

Figure 13-39 IRQCLR Register
3130292827262524
DMA_BUS_ERRKEY_ST_WR_ERRKEY_ST_RD_ERRRESERVED
W-0hW-0hW-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA_IN_DONERESULT_AVAIL
R-0hW-0hW-0h
Table 13-56 IRQCLR Register Field Descriptions
BitFieldTypeResetDescription
31DMA_BUS_ERRW0hIf 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared.
30KEY_ST_WR_ERRW0hIf 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared.
29KEY_ST_RD_ERRW0hIf 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared.
28-2RESERVEDR0hReserved
1DMA_IN_DONEW0hIf 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared.
0RESULT_AVAILW0hIf 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared.

13.9.1.38 IRQSET Register (Offset = 78Ch) [Reset = 00000000h]

IRQSET is shown in Figure 13-40 and described in Table 13-57.

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Interrupt Set

Figure 13-40 IRQSET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA_IN_DONERESULT_AVAIL
R-0hW-0hW-0h
Table 13-57 IRQSET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1DMA_IN_DONEW0hIf 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set.
Writing 0 has no effect.
0RESULT_AVAILW0hIf 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set.
Writing 0 has no effect.

13.9.1.39 IRQSTAT Register (Offset = 790h) [Reset = 00000000h]

IRQSTAT is shown in Figure 13-41 and described in Table 13-58.

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Interrupt Status

Figure 13-41 IRQSTAT Register
3130292827262524
DMA_BUS_ERRKEY_ST_WR_ERRKEY_ST_RD_ERRRESERVED
R-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA_IN_DONERESULT_AVAIL
R-0hR-0hR-0h
Table 13-58 IRQSTAT Register Field Descriptions
BitFieldTypeResetDescription
31DMA_BUS_ERRR0hThis bit is set when a DMA bus error is detected during a DMA operation. The value of this register is held until it is cleared via IRQCLR.DMA_BUS_ERR
Note: This error is asserted if an error is detected on the AHB master interface during a DMA operation.
Note: This is not an interrupt source.
30KEY_ST_WR_ERRR0hThis bit is set when a write error is detected during the DMA write operation to the key store memory. The value of this register is held until it is cleared via IRQCLR.KEY_ST_WR_ERR
Note: This error is asserted if a DMA operation does not cover a full key area or more areas are written than expected.
Note: This is not an interrupt source.
29KEY_ST_RD_ERRR0hThis bit will be set when a read error is detected during the read of a key from the key store, while copying it to the AES engine. The value of this register is held until it is cleared via IRQCLR.KEY_ST_RD_ERR.
Note: This error is asserted if a key location is selected in the key store that is not available.
Note: This is not an interrupt source.
28-2RESERVEDR0hReserved
1DMA_IN_DONER0hThis bit returns the status of DMA data in done interrupt.
0RESULT_AVAILR0hThis bit is set high when the Crypto peripheral has a result available.

13.9.1.40 HWVER Register (Offset = 7FCh) [Reset = 91118778h]

HWVER is shown in Figure 13-42 and described in Table 13-59.

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CTRL Module Version

Figure 13-42 HWVER Register
31302928272625242322212019181716
RESERVEDHW_MAJOR_VERHW_MINOR_VERHW_PATCH_LVL
R-0hR-1hR-1hR-1h
1514131211109876543210
VER_NUM_COMPLVER_NUM
R-87hR-78h
Table 13-59 HWVER Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-24HW_MAJOR_VERR1hMajor version number
23-20HW_MINOR_VERR1hMinor version number
19-16HW_PATCH_LVLR1hPatch level, starts at 0 at first delivery of this version.
15-8VER_NUM_COMPLR87hThese bits simply contain the complement of VER_NUM (0x87), used by a driver to ascertain that the Crypto peripheral register is indeed read.
7-0VER_NUMR78hThe version number for the Crypto peripheral, this field contains the value 120 (decimal) or 0x78.