SWCU191 February   2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA

 

  1. 1 Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  2. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Analog Peripherals
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  3. 3 Arm® Cortex®-M4 Processor
    1. 3.1 Arm® Cortex®-M4 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Arm® Cortex®-M4 System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4 Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4 Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Arm® Cortex®-M4 Processor Registers
      1. 3.7.1 CPU_DWT Registers
      2. 3.7.2 CPU_FPB Registers
      3. 3.7.3 CPU_ITM Registers
      4. 3.7.4 CPU_SCS Registers
      5. 3.7.5 CPU_TPIU Registers
  4. 4 Memory Map
    1. 4.1 Memory Map
  5. 5 Arm® Cortex®-M4 Peripherals
    1. 5.1 Arm® Cortex®-M4 Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  6. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  7. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  8. 8 Power, Reset and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 OSC_DIG Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  9. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  10. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM Registers
  11. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  13. 13Cryptography
    1. 13.1 AES Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master Transfer Protection
          1. 13.5.4.2.1 Master Transfer Protection Control
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Encryption and Decryption
        1. 13.7.3.1 Key Store
          1. 13.7.3.1.1 Load Keys From External Memory
        2. 13.7.3.2 Basic AES Modes
          1. 13.7.3.2.1 AES-ECB
          2. 13.7.3.2.2 AES-CBC
          3. 13.7.3.2.3 AES-CTR
          4. 13.7.3.2.4 Programming Sequence With DMA Data
        3. 13.7.3.3 CBC-MAC
          1. 13.7.3.3.1 Programming Sequence for CBC-MAC
        4. 13.7.3.4 AES-CCM
          1. 13.7.3.4.1 Programming Sequence for AES-CCM
      4. 13.7.4 Exceptions Handling
        1. 13.7.4.1 Soft Reset
        2. 13.7.4.2 External Port Errors
        3. 13.7.4.3 Key Store Errors
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  14. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  15. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 μDMA Registers
  16. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  17. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  18. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  19. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  20. 20AUX Domain Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
      3. 20.2.3 SCE Clock Emulation
    3. 20.3 Digital Peripheral Modules
      1. 20.3.1 Overview
        1. 20.3.1.1 DDI Control-Configuration
      2. 20.3.2 AIODIO
        1. 20.3.2.1 Introduction
        2. 20.3.2.2 Functional Description
          1. 20.3.2.2.1 Mapping to DIO Pins
          2. 20.3.2.2.2 Configuration
          3. 20.3.2.2.3 GPIO Mode
          4. 20.3.2.2.4 Input Buffer
          5. 20.3.2.2.5 Data Output Source
      3. 20.3.3 SMPH
        1. 20.3.3.1 Introduction
        2. 20.3.3.2 Functional Description
        3. 20.3.3.3 Semaphore Allocation in TI Software
      4. 20.3.4 Time-to-Digital Converter (TDC)
        1. 20.3.4.1 Introduction
        2. 20.3.4.2 Functional Description
          1. 20.3.4.2.1 Command
          2. 20.3.4.2.2 Conversion Time Configuration
          3. 20.3.4.2.3 Status and Result
          4. 20.3.4.2.4 Clock Source Selection
            1. 20.3.4.2.4.1 Counter Clock
            2. 20.3.4.2.4.2 Reference Clock
          5. 20.3.4.2.5 Start and Stop Events
          6. 20.3.4.2.6 Prescaler
        3. 20.3.4.3 Supported Measurement Types
          1. 20.3.4.3.1 Measure Pulse Width
          2. 20.3.4.3.2 Measure Frequency
          3. 20.3.4.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.3.4.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.3.4.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.3.4.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.3.4.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.3.4.3.4 Pulse Counting
      5. 20.3.5 Timer01
        1. 20.3.5.1 Introduction
        2. 20.3.5.2 Functional Description
    4. 20.4 Analog Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 ADI Control-Configuration
        2. 20.4.1.2 Block Diagram
      2. 20.4.2 Analog-to-Digital Converter (ADC)
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Input Selection and Scaling
          2. 20.4.2.2.2 Reference Selection
          3. 20.4.2.2.3 ADC Sample Mode
          4. 20.4.2.2.4 ADC Clock Source
          5. 20.4.2.2.5 ADC Trigger
          6. 20.4.2.2.6 Sample FIFO
          7. 20.4.2.2.7 µDMA Interface
          8. 20.4.2.2.8 Resource Ownership and Usage
      3. 20.4.3 COMPA
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
          1. 20.4.3.2.1 Input Selection
          2. 20.4.3.2.2 Reference Selection
          3. 20.4.3.2.3 LPM Bias and COMPA Enable
          4. 20.4.3.2.4 Resource Ownership and Usage
      4. 20.4.4 COMPB
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 Input Selection
          2. 20.4.4.2.2 Reference Selection
          3. 20.4.4.2.3 Resource Ownership and Usage
            1. 20.4.4.2.3.1 System CPU Wakeup
      5. 20.4.5 Reference DAC
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Reference Selection
          2. 20.4.5.2.2 Output Voltage Control and Range
          3. 20.4.5.2.3 Sample Clock
            1. 20.4.5.2.3.1 Automatic Phase Control
            2. 20.4.5.2.3.2 Manual Phase Control
            3. 20.4.5.2.3.3 Operational Mode Dependency
          4. 20.4.5.2.4 Output Selection
            1. 20.4.5.2.4.1 Buffer
            2. 20.4.5.2.4.2 External Load
            3. 20.4.5.2.4.3 COMPA_REF
            4. 20.4.5.2.4.4 COMPB_REF
          5. 20.4.5.2.5 LPM Bias
          6. 20.4.5.2.6 Resource Ownership and Usage
      6. 20.4.6 ISRC
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
          1. 20.4.6.2.1 Programmable Current
          2. 20.4.6.2.2 Voltage Reference
          3. 20.4.6.2.3 ISRC Enable
          4. 20.4.6.2.4 Temperature Dependency
          5. 20.4.6.2.5 Resource Ownership and Usage
    5. 20.5 Event Routing and Usage
      1. 20.5.1 AUX Event Bus
        1. 20.5.1.1 Event Signals
        2. 20.5.1.2 Event Subscribers
          1. 20.5.1.2.1 Event Detection
            1. 20.5.1.2.1.1 Detection of Asynchronous Events
            2. 20.5.1.2.1.2 Detection of Synchronous Events
      2. 20.5.2 Event Observation on External Pin
      3. 20.5.3 Events From MCU Domain
      4. 20.5.4 Events to MCU Domain
      5. 20.5.5 Events From AON Domain
      6. 20.5.6 Events to AON Domain
      7. 20.5.7 µDMA Interface
    6. 20.6 AUX Domain Peripheral Registers
      1. 20.6.1 ADI_4_AUX Registers
      2. 20.6.2 AUX_AIODIO Registers
      3. 20.6.3 AUX_EVCTL Registers
      4. 20.6.4 AUX_SMPH Registers
      5. 20.6.5 AUX_TDC Registers
      6. 20.6.6 AUX_TIMER01 Registers
      7. 20.6.7 AUX_ANAIF Registers
      8. 20.6.8 AUX_SYSIF Registers
  21. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  22. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  23. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  24. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  25. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  26. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
        1.       Revision History

17.4.1 AON_RTC Registers

#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_TABLE_1 lists the memory-mapped registers for the AON_RTC registers. All register offset addresses not listed in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 17-1 AON_RTC Registers
OffsetAcronymRegister NameSection
0hCTLControl#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CTL
4hEVFLAGSEvent Flags, RTC Status#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_EVFLAGS
8hSECSecond Counter Value, Integer Part#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SEC
ChSUBSECSecond Counter Value, Fractional Part#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SUBSEC
10hSUBSECINCSubseconds Increment#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SUBSECINC
14hCHCTLChannel Configuration#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CHCTL
18hCH0CMPChannel 0 Compare Value#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH0CMP
1ChCH1CMPChannel 1 Compare Value#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH1CMP
20hCH2CMPChannel 2 Compare Value#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH2CMP
24hCH2CMPINCChannel 2 Compare Value Auto-increment#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH2CMPINC
28hCH1CAPTChannel 1 Capture Value#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH1CAPT
2ChSYNCAON Synchronization#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SYNC
30hTIMECurrent Counter Value#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_TIME
34hSYNCLFSynchronization to SCLK_LF#CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SYNCLF

Complex bit access types are encoded to fit into small table cells. #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_LEGEND shows the codes that are used for access types in this section.

Table 17-2 AON_RTC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

17.4.1.1 CTL Register (Offset = 0h) [Reset = 00000000h]

CTL is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CTL_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CTL_TABLE.

Return to the Summary Table.

Control
This register contains various bitfields for configuration of RTC
RTL Name = CONFIG

Figure 17-2 CTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCOMB_EV_MASK
R-0hR/W-0h
15141312111098
RESERVEDEV_DELAY
R-0hR/W-0h
76543210
RESETRESERVEDRTC_4KHZ_ENRTC_UPD_ENEN
W1C-0hR-0hR/W-0hR/W-0hR/W-0h
Table 17-3 CTL Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-16COMB_EV_MASKR/W0hEventmask selecting which delayed events that form the combined event.
0h = No event is selected for combined event.
1h = Use Channel 0 delayed event in combined event
2h = Use Channel 1 delayed event in combined event
4h = Use Channel 2 delayed event in combined event
15-12RESERVEDR0hReserved
11-8EV_DELAYR/W0hNumber of SCLK_LF clock cycles waited before generating delayed events. (Common setting for all RTC cannels) the delayed event is delayed
0h = No delay on delayed event
1h = Delay by 1 clock cycles
2h = Delay by 2 clock cycles
3h = Delay by 4 clock cycles
4h = Delay by 8 clock cycles
5h = Delay by 16 clock cycles
6h = Delay by 32 clock cycles
7h = Delay by 48 clock cycles
8h = Delay by 64 clock cycles
9h = Delay by 80 clock cycles
Ah = Delay by 96 clock cycles
Bh = Delay by 112 clock cycles
Ch = Delay by 128 clock cycles
Dh = Delay by 144 clock cycles
7RESETW1C0hRTC Counter reset.
Writing 1 to this bit will reset the RTC counter.
This bit is cleared when reset takes effect
6-3RESERVEDR0hReserved
2RTC_4KHZ_ENR/W0hRTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 which is used by AUX timer.
0: RTC_4KHZ signal is forced to 0
1: RTC_4KHZ is enabled ( provied that RTC is enabled EN)
1RTC_UPD_ENR/W0hRTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is SCLK_LF divided by 2
0: RTC_UPD signal is forced to 0
1: RTC_UPD signal is toggling @16 kHz
0ENR/W0hEnable RTC counter
0: Halted (frozen)
1: Running

17.4.1.2 EVFLAGS Register (Offset = 4h) [Reset = 00000000h]

EVFLAGS is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_EVFLAGS_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_EVFLAGS_TABLE.

Return to the Summary Table.

Event Flags, RTC Status
This register contains event flags from the 3 RTC channels. Each flag will be cleared when writing a '1' to the corresponding bitfield.

Figure 17-3 EVFLAGS Register
31302928272625242322212019181716
RESERVEDCH2
R-0hR/W1C-0h
1514131211109876543210
RESERVEDCH1RESERVEDCH0
R-0hR/W1C-0hR-0hR/W1C-0h
Table 17-4 EVFLAGS Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16CH2R/W1C0hChannel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or passes the CH2CMP value.
An event will be scheduled to occur as soon as possible when writing to CH2CMP provided that the channel is enabled and the new value matches any time between next RTC value and 1 second in the past
Writing 1 clears this flag.
AUX_SCE can read the flag through AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and clear it using AUX_SYSIF:RTCEVCLR.RTC_CH2_EV_CLR.
15-9RESERVEDR0hReserved
8CH1R/W1C0hChannel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following:
- CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP value.
- CHCTL.CH1_CAPT_EN = 1 and capture occurs.
An event will be scheduled to occur as soon as possible when writing to CH1CMP provided that the channel is enabled, in compare mode and the new value matches any time between next RTC value and 1 second in the past.
Writing 1 clears this flag.
7-1RESERVEDR0hReserved
0CH0R/W1C0hChannel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or passes the CH0CMP value.
An event will be scheduled to occur as soon as possible when writing to CH0CMP provided that the channels is enabled and the new value matches any time between next RTC value and 1 second in the past.
Writing 1 clears this flag.

17.4.1.3 SEC Register (Offset = 8h) [Reset = 00000000h]

SEC is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SEC_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SEC_TABLE.

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Second Counter Value, Integer Part

Figure 17-4 SEC Register
313029282726252423222120191817161514131211109876543210
VALUE
R/W-0h
Table 17-5 SEC Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER/W0hUnsigned integer representing Real Time Clock in seconds.
When reading this register the content of SUBSEC.VALUE is simultaneously latched. A consistent reading of the combined Real Time Clock can be obtained by first reading this register, then reading SUBSEC register.

17.4.1.4 SUBSEC Register (Offset = Ch) [Reset = 00000000h]

SUBSEC is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SUBSEC_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SUBSEC_TABLE.

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Second Counter Value, Fractional Part

Figure 17-5 SUBSEC Register
313029282726252423222120191817161514131211109876543210
VALUE
R/W-0h
Table 17-6 SUBSEC Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER/W0hUnsigned integer representing Real Time Clock in fractions of a second (VALUE/232 seconds) at the time when SEC register was read.
Examples :
- 0x0000_0000 = 0.0 sec
- 0x4000_0000 = 0.25 sec
- 0x8000_0000 = 0.5 sec
- 0xC000_0000 = 0.75 sec

17.4.1.5 SUBSECINC Register (Offset = 10h) [Reset = 00800000h]

SUBSECINC is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SUBSECINC_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SUBSECINC_TABLE.

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Subseconds Increment
Value added to SUBSEC.VALUE on every SCLK_LFclock cycle.

Figure 17-6 SUBSECINC Register
313029282726252423222120191817161514131211109876543210
RESERVEDVALUEINC
R-0hR-00800000h
Table 17-7 SUBSECINC Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0VALUEINCR00800000hThis value compensates for a SCLK_LF clock which has an offset from 32768 Hz.
The compensation value can be found as 238 / freq, where freq is SCLK_LF clock frequency in Hertz
This value is added to SUBSEC.VALUE on every cycle, and carry of this is added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a hidden 6-bit register that generates a carry into the above mentioned addition on overflow.
The default value corresponds to incrementing by precisely 1/32768 of a second.
NOTE: This register is read only. Modification of the register value must be done using registers AUX_SYSIF:RTCSUBSECINC0 , AUX_SYSIF:RTCSUBSECINC1 and AUX_SYSIF:RTCSUBSECINCCTL

17.4.1.6 CHCTL Register (Offset = 14h) [Reset = 00000000h]

CHCTL is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CHCTL_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CHCTL_TABLE.

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Channel Configuration

Figure 17-7 CHCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCH2_CONT_ENRESERVEDCH2_EN
R-0hR/W-0hR-0hR/W-0h
15141312111098
RESERVEDCH1_CAPT_ENCH1_EN
R-0hR/W-0hR/W-0h
76543210
RESERVEDCH0_EN
R-0hR/W-0h
Table 17-8 CHCTL Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18CH2_CONT_ENR/W0hSet to enable continuous operation of Channel 2
17RESERVEDR0hReserved
16CH2_ENR/W0hRTC Channel 2 Enable
0: Disable RTC Channel 2
1: Enable RTC Channel 2
15-10RESERVEDR0hReserved
9CH1_CAPT_ENR/W0hSet Channel 1 mode
0: Compare mode (default)
1: Capture mode
8CH1_ENR/W0hRTC Channel 1 Enable
0: Disable RTC Channel 1
1: Enable RTC Channel 1
7-1RESERVEDR0hReserved
0CH0_ENR/W0hRTC Channel 0 Enable
0: Disable RTC Channel 0
1: Enable RTC Channel 0

17.4.1.7 CH0CMP Register (Offset = 18h) [Reset = 00000000h]

CH0CMP is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH0CMP_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH0CMP_TABLE.

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Channel 0 Compare Value

Figure 17-8 CH0CMP Register
313029282726252423222120191817161514131211109876543210
VALUE
R/W-0h
Table 17-9 CH0CMP Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER/W0hRTC Channel 0 compare value.
Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value.
The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value.
Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value.
Example:
To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000
*) It can take up to one SCLK_LF clock cycles before event occurs due to synchronization.

17.4.1.8 CH1CMP Register (Offset = 1Ch) [Reset = 00000000h]

CH1CMP is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH1CMP_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH1CMP_TABLE.

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Channel 1 Compare Value

Figure 17-9 CH1CMP Register
313029282726252423222120191817161514131211109876543210
VALUE
R/W-0h
Table 17-10 CH1CMP Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER/W0hRTC Channel 1 compare value.
Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value.
The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value.
Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value.
Example:
To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000
*) It can take up to one SCLK_LF clock cycles before event occurs due to synchronization.

17.4.1.9 CH2CMP Register (Offset = 20h) [Reset = 00000000h]

CH2CMP is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH2CMP_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH2CMP_TABLE.

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Channel 2 Compare Value

Figure 17-10 CH2CMP Register
313029282726252423222120191817161514131211109876543210
VALUE
R/W-0h
Table 17-11 CH2CMP Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER/W0hRTC Channel 2 compare value.
Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value.
The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value.
Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value.
Example:
To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000
*) It can take up to one SCLK_LF clock cycles before event occurs due to synchronization.

17.4.1.10 CH2CMPINC Register (Offset = 24h) [Reset = 00000000h]

CH2CMPINC is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH2CMPINC_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH2CMPINC_TABLE.

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Channel 2 Compare Value Auto-increment
This register is primarily used to generate periodical wake-up for the AUX_SCE module, through the [AUX_EVCTL.EVSTAT0.AON_RTC] event.

Figure 17-11 CH2CMPINC Register
313029282726252423222120191817161514131211109876543210
VALUE
R/W-0h
Table 17-12 CH2CMPINC Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER/W0hIf CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every channel 2 compare event.

17.4.1.11 CH1CAPT Register (Offset = 28h) [Reset = 00000000h]

CH1CAPT is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH1CAPT_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_CH1CAPT_TABLE.

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Channel 1 Capture Value
If CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1, capture occurs on each rising edge of the event selected in AON_EVENT:RTCSEL.

Figure 17-12 CH1CAPT Register
313029282726252423222120191817161514131211109876543210
SECSUBSEC
R-0hR-0h
Table 17-13 CH1CAPT Register Field Descriptions
BitFieldTypeResetDescription
31-16SECR0hValue of SEC.VALUE bits 15:0 at capture time.
15-0SUBSECR0hValue of SUBSEC.VALUE bits 31:16 at capture time.

17.4.1.12 SYNC Register (Offset = 2Ch) [Reset = 00000000h]

SYNC is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SYNC_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SYNC_TABLE.

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AON Synchronization
This register is used for synchronizing between MCU and entire AON domain.

Figure 17-13 SYNC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDWBUSY
R-0hR/W-0h
Table 17-14 SYNC Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0WBUSYR/W0hThis register will always return 0,- however it will not return the value until there are no outstanding write requests between MCU and AON
Note: Writing to this register prior to reading will force a wait until next SCLK_MF edge. This is recommended for syncing read registers from AON when waking up from sleep
Failure to do so may result in reading AON values from prior to going to sleep

17.4.1.13 TIME Register (Offset = 30h) [Reset = 00000000h]

TIME is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_TIME_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_TIME_TABLE.

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Current Counter Value

Figure 17-14 TIME Register
313029282726252423222120191817161514131211109876543210
SEC_LSUBSEC_H
R-0hR-0h
Table 17-15 TIME Register Field Descriptions
BitFieldTypeResetDescription
31-16SEC_LR0hReturns the lower halfword of SEC register.
15-0SUBSEC_HR0hReturns the upper halfword of SUBSEC register.

17.4.1.14 SYNCLF Register (Offset = 34h) [Reset = 00000000h]

SYNCLF is shown in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SYNCLF_FIGURE and described in #CC26_AON_RTC_CC26_AON_RTC_AON_RTC_RMAP_CC26_AON_RTC_ALL_SYNCLF_TABLE.

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Synchronization to SCLK_LF
This register is used for synchronizing MCU to positive or negative edge of SCLK_LF.

Figure 17-15 SYNCLF Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPHASE
R-0hR-0h
Table 17-16 SYNCLF Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0PHASER0hThis bit will always return the SCLK_LF phase. The return will delayed until a positive or negative edge of SCLK_LF is seen.
0: Falling edge of SCLK_LF
1: Rising edge of SCLK_LF