SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
The common RX FIFO is a 16 bit wide, 8 location deep, first-in-first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSI:DR register.
When configured as a master or slave, serial data received through the SSIn_RX pin is registered before parallel loading into the attached slave or master RX FIFO, respectively.