SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
23.4.4.7 MICROWIRE Frame Format
Figure 23-10 shows the MICROWIRE frame format for a single frame. Figure 23-11 shows the same format when back-to-back frames are transmitted.
Figure 23-10 MICROWIRE Frame Format (Single Frame)MICROWIRE format is similar to SPI format, except that transmission is half-duplex and uses a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, the SSI does not receive incoming data. After the message is sent, the off-chip slave decodes it and waits one serial clock after the last bit of the 8-bit control message is sent. The off-chip slave then responds with the required data. The returned data is 4 to 16 bits long, making the total frame length anywhere from 13 to 25 bits.
In this configuration, the following occurs during idle periods:
- SSIn_CLK is forced low
- SSIn_FSS is forced high
- The transmit data line SSIn_TX is arbitrarily forced low
Writing a control byte to the TX FIFO triggers a transmission. The falling edge of SSIn_FSS transfers the value in the bottom entry of the TX FIFO to the serial shift register of the transmit logic and shifts the MSB of the 8-bit control frame out onto the SSIn_TX pin. SSIn_FSS remains low for the duration of the frame transmission. The SSIn_RX pin remains in the tri-state condition during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on each rising edge of SSIn_CLK. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait state and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIn_RX line on the falling edge of SSIn_CLK. The SSI latches each bit on the rising edge of SSIn_CLK. At the end of the frame for single transfers, the SSIFss signal is pulled high one clock period after the last bit is latched in the receive serial shifter transferring the data to the RX FIFO.
The off-chip slave device can place the receive line in a tri-state condition either on the falling edge of SSIn_CLK (after the LSB has been latched by the receive shifter), or when the SSIn_FSS pin goes high.
For continuous transfers, data transmission begins and ends like a single transfer, but the SSIn_FSS line is held low and data transmits back-to-back. The control byte of the next frame follows the LSB of the received data from the current frame. After the LSB of the frame is latched into the SSI, each received value is transferred from the receive shifter on the falling edge of SSIn_CLK.
Figure 23-11 MICROWIRE Frame Format (Continuous Transfer)In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIn_CLK after SSIFss has gone low. Masters driving a free-running SSIn_CLK must ensure that the SSIFss signal has sufficient setup and hold margins compared to the rising edge of SSIn_CLK.
Figure 23-12 shows these setup and hold time requirements. With respect to the SSIn_CLK rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIn_FSS must have a setup of at least two times the period of SSIn_CLK on which the SSI operates. With respect to the SSIn_CLK rising edge previous to this edge, SSIn_FSS must have a hold of at least one SSIn_CLK period.
Figure 23-12 MICROWIRE Frame Format, SSIFss Input Setup, and Hold Requirements