SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The slave module can generate an interrupt when data is received or requested. This interrupt is enabled by setting the in the I2C Slave Interrupt Mask register (I2C:SIMR). Software determines whether the module must write (transmit) or read (receive) data from the I2C Slave Data register (I2C:SDR) DATAIM bit, by checking the RREQ and TREQ bits of the I2C Slave Control and Status register (I2C:SSTAT). If the slave module is in receive mode and the first byte of a transfer is received, the FBR and RREQ bits are set. The interrupt is cleared by setting the I2C Slave Interrupt Clear register (I2C:SICR) DATAIC bit.
In addition, the slave module generates an interrupt when a Start and a Stop condition is detected. These interrupts are enabled by setting the I2C:SIMR register STARTIM and STOPIM bits; these interrupts are cleared by setting the I2C:SICR register STOPIC and STARTIC bits to 1.
If the application does not require the use of interrupts, the raw interrupt status is always visible through the I2C Slave Raw Interrupt Status register (I2C:SRIS).