SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Table 6-5 lists the input events for the MCU event fabric. The sources for these events are considered level-triggered active high.
Event Number | Event Enumeration | Description |
---|---|---|
0x0 | NONE | Always inactive (LOW) |
0x1 | AON_PROG0 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV |
0x2 | AON_PROG1 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV |
0x3 | AON_PROG2 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV |
0x4 | AON_GPIO_EDGE | Edge detect event from IOC. Configured by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings |
0x5 | RESERVED | |
0x6 | RESERVED | |
0x7 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting |
0x8 | I2S_IRQ | Interrupt event from I2S |
0x9 | I2C_IRQ | Interrupt event from I2C |
0xA | AON_AUX_SWEV0 | AUX software event 0, AUX_EVCTL:SWEVSET.SWEV0 |
0xB | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS.* |
0xC | GPT2A | GPT2A interrupt event, controlled by GPT2:TAMR.* |
0xD | GPT2B | GPT2B interrupt event, controlled by GPT2:TBMR.* |
0xE | GPT3A | GPT3A interrupt event, controlled by GPT3:TAMR.* |
0xF | GPT3B | GPT3B interrupt event, controlled by GPT3:TBMR.* |
0x10 | GPT0A | GPT0A interrupt event, controlled by GPT0:TAMR.* |
0x11 | GPT0B | GPT0B interrupt event, controlled by GPT0:TBMR.* |
0x12 | GPT1A | GPT1A interrupt event, controlled by GPT1:TAMR.* |
0x13 | GPT1B | GPT1B interrupt event, controlled by GPT1:TBMR.* |
0x14 | DMA_CH0_DONE | DMA done for software-triggered UDMA channel 0, see UDMA0:SOFTREQ.* in Section 15.5.1 |
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT |
0x16 | DMA_CH18_DONE | DMA done for software-triggered UDMA channel 18, see UDMA0:SOFTREQ.* in Section 15.5.1 |
0x17 | RESERVED | |
0x18 | WDT_IRQ | Watchdog interrupt event, controlled by WDT:CTL.INTEN |
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgment interrupt, equivalent to RFC_DBELL:RFACKIFG.ACKFLAG. |
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG.* |
0x1B | RFC_CPE_0 | Combined interrupt for CPE-generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG.*. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG.* can trigger a RFC_CPE_0 event. |
0x1C | AUX_SWEV0 | AUX software
event 0, triggered by AUX_EVCTL:SWEVSET.SWEV0, also available as
AUX_EVENT0 AON wake-up event. MCU domain wake-up control AON_EVENT:MCUWUSEL.* AUX domain wake-up control AON_EVENT:AUXWUSEL.* |
0x1D | AUX_SWEV1 | AUX software
event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as
AUX_EVENT2 AON wake-up event. MCU domain wake-up control AON_EVENT:MCUWUSEL.* AUX domain wake-up control AON_EVENT:AUXWUSEL.* |
0x1E | RFC_CPE_1 | Combined interrupt for CPE-generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG.*. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG.* can trigger a RFC_CPE_1 event. |
0x1F to 0x21 | RESERVED | |
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS.*. |
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS.*. |
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS.*. |
0x25 | RESERVED | Always 0 (LOW) |
0x26 | DMA_ERR | DMA bus error, corresponds to UDMA0:ERROR.STATUS |
0x27 | DMA_DONE_COMB | Combined DMA done corresponding flags are here UDMA0:REQDONE.* |
0x28 | SSI0_RX_DMABREQ | SSI0 RX DMA burst request, controlled by SSI0:DMACR.RXDMAE |
0x29 | SSI0_RX_DMASREQ | SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE |
0x2A | SSI0_TX_DMABREQ | SSI0 TX DMA burst request, controlled by SSI0:DMACR.TXDMAE |
0x2B | SSI0_TX_DMASREQ | SSI0 TX DMA single request, controlled by SSI0:DMACR.TXDMAE |
0x2C | SSI1_RX_DMABREQ | SSI1 RX DMA burst request, controlled by SSI0:DMACR.RXDMAE |
0x2D | SSI1_RX_DMASREQ | SSI1 RX DMA single request, controlled by SSI0:DMACR.RXDMAE |
0x2E | SSI1_TX_DMABREQ | SSI1 TX DMA burst request, controlled by SSI0:DMACR.TXDMAE |
0x2F | SSI1_TX_DMASREQ | SSI1 TX DMA single request, controlled by SSI0:DMACR.TXDMAE |
0x30 | UART0_RX_DMABREQ | UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE |
0x31 | UART0_RX_DMASREQ | UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE |
0x32 | UART0_TX_DMABREQ | UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE |
0x33 | UART0_TX_DMASREQ | UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE |
0x34 to 0x37 | RESERVED | Always 0 |
0x38 | RESERVED | |
0x39 | RESERVED | |
0x3A | RESERVED | |
0x3B | RESERVED | |
0x3C | RESERVED | |
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT. |
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT. |
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT. |
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT. |
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT. |
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT. |
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT. |
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT. |
0x45 to 0x4C | TIE_LOW | Not used; tied to 0 (LOW) |
0x4D | GPT0A_DMABREQ | GPT 0A DMA trigger event. Configured by GPT0:DMAEV.*. |
0x4E | GPT0B_DMABREQ | GPT 0B DMA trigger event. Configured by GPT0:DMAEV.*. |
0x4F | GPT1A_DMABREQ | GPT 1A DMA trigger event. Configured by GPT1:DMAEV.*. |
0x50 | GPT1B_DMABREQ | GPT 1B DMA trigger event. Configured by GPT1:DMAEV.*. |
0x51 | GPT2A_DMABREQ | GPT 2A DMA trigger event. Configured by GPT2:DMAEV.*. |
0x52 | GPT2B_DMABREQ | GPT 2B DMA trigger event. Configured by GPT2:DMAEV.*. |
0x53 | GPT3A_DMABREQ | GPT 3A DMA trigger event. Configured by GPT3:DMAEV.*. |
0x54 | GPT3B_DMABREQ | GPT 3B DMA trigger event. Configured by GPT3:DMAEV.*. |
0x55 | PORT_EVENT0 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with **ENUM** **PORT_EVENT0** are routed here. |
0x56 | PORT_EVENT1 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with PORT_EVENT1 are routed here. |
0x57 | PORT_EVENT2 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with PORT_EVENT2 are routed here. |
0x58 | PORT_EVENT3 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with PORT_EVENT3 are routed here. |
0x59 | PORT_EVENT4 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 are routed here. |
0x5A | PORT_EVENT5 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with PORT_EVENT4 are routed here. |
0x5B | PORT_EVENT6 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with PORT_EVENT6 are routed here. |
0x5C | PORT_EVENT7 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with PORT_EVENT7 are routed here. |
0x5D | CRYPTO_RESULT_AVAIL_IRQ | CRYPTO result available interrupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL |
0x5E | CRYPTO_DMA_DONE_IRQ | CRYPTO DMA input done event, the corresponding flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by CRYPTO:IRQEN.DMA_IN_DONE |
0x5F | RFC_IN_EV4 | RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4 |
0x60 | RFC_IN_EV5 | RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5 |
0x61 | RFC_IN_EV6 | RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6 |
0x62 | RFC_IN_EV7 | RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7 |
0x63 | WDT_NMI | WATCHDOG nonmaskable interrupt event, controlled by WDT:CTL.INTTYPE |
0x64 | SWEV0 | Software event 0, triggered by SWEV.SWEV0 |
0x65 | SWEV1 | Software event 1, triggered by SWEV.SWEV1 |
0x66 | SWEV2 | Software event 2, triggered by SWEV.SWEV2 |
0x67 | SWEV3 | Software event 3, triggered by SWEV.SWEV3 |
0x68 | TRNG_IRQ | TRNG Interrupt event, controlled by TRNG:IRQEN.EN |
0x69 | AUX_AON_WU_EV | AON wake-up event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV. |
0x6A | AUX_COMPA | AUX COMP A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA. |
0x6B | AUX_COMPB | AUX COMP B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB. |
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE. |
0x6D | AUX_TIMER0_EV | AUX TIMER 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV. |
0x6E | AUX_TIMER1_EV | AUX TIMER 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV. |
0x6F | AUX_SMPH_AUTOTAKE_DONE | Auto-take event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE.*. |
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE |
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL |
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 |
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS.ADC* |
0x74 | AUX_SW_DMABREQ | AUX observation loopback |
0x75 | AUX_DMASREQ | DMA single request event from AUX, configured by AUX_EVCTL:DMACTL.* |
0x76 | AUX_DMABREQ | DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL.* |
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN |
0x78 | CPU_HALTED | CPU halted |
0x79 | ALWAYS_ACTIVE | Always asserted (HIGH) |