SWCU192 User guide

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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690
1. 691
2. 692
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695
1. 696
2. 697
3. 698
4. 699
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5. 711
6. 712
7. 713
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715
1. 716
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3. 718
4. 719
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6. 736
7. 737
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1. 740
2. 741
3. 742
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    1. 750
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    1. 756
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4. 758
5. 759
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761
1. 762
2. 763
3. 764
4. 765
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    1. 777
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    1. 779
    2. 780
5. 781
  1. 782
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6. 789
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7. 794
8. 795
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9. 798
  1. 799
800
1. 801
  1. 802
2. 803
  1. 804
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  3. 806
    1. 807
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    1. 811
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    3. 813
3. 814
  1. 815
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    1. 817
    2. 818
    3. 819
    4. 820
    5. 821
      1. 822
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      3. 824
    6. 825
      1. 826
    7. 827
      1. 828
      2. 829
      3. 830
      4. 831
    8. 832
  3. 833
    1. 834
      1. 835
      2. 836
      3. 837
      4. 838
      5. 839
      6. 840
      7. 841
      8. 842
      9. 843
      10. 844
      11. 845
      12. 846
      13. 847
      14. 848
    2. 849
      1. 850
      2. 851
      3. 852
      4. 853
      5. 854
      6. 855
      7. 856
      8. 857
      9. 858
      10. 859
      11. 860
      12. 861
      13. 862
      14. 863
      15. 864
      16. 865
      17. 866
      18. 867
      19. 868
      20. 869
  4. 870
    1. 871
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    3. 873
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4. 876
  1. 877
    1. 878
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  2. 883
    1. 884
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5. 886
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    1. 888
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    3. 890
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    1. 894
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  4. 896
    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
      4. 903
      5. 904
    2. 905
    3. 906
    4. 907
    5. 908
    6. 909
  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
    5. 915
    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
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8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
    3. 939
    4. 940
  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
    2. 947
    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

20.8.9 AUX_SYSIF Registers

#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_TABLE_1 lists the memory-mapped registers for the AUX_SYSIF registers. All register offset addresses not listed in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 20-174 AUX_SYSIF Registers

Offset	Acronym	Register Name	Section
0h	OPMODEREQ	Operational Mode Request	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_OPMODEREQ
4h	OPMODEACK	Operational Mode Acknowledgement	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_OPMODEACK
8h	PROGWU0CFG	Programmable Wakeup 0 Configuration	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU0CFG
Ch	PROGWU1CFG	Programmable Wakeup 1 Configuration	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU1CFG
10h	PROGWU2CFG	Programmable Wakeup 2 Configuration	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU2CFG
14h	PROGWU3CFG	Programmable Wakeup 3 Configuration	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU3CFG
18h	SWWUTRIG	Software Wakeup Triggers	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_SWWUTRIG
1Ch	WUFLAGS	Wakeup Flags	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_WUFLAGS
20h	WUFLAGSCLR	Wakeup Flags Clear	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_WUFLAGSCLR
24h	WUGATE	Wakeup Gate	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_WUGATE
28h	VECCFG0	Vector Configuration 0	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG0
2Ch	VECCFG1	Vector Configuration 1	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG1
30h	VECCFG2	Vector Configuration 2	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG2
34h	VECCFG3	Vector Configuration 3	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG3
38h	VECCFG4	Vector Configuration 4	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG4
3Ch	VECCFG5	Vector Configuration 5	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG5
40h	VECCFG6	Vector Configuration 6	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG6
44h	VECCFG7	Vector Configuration 7	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG7
48h	EVSYNCRATE	Event Synchronization Rate	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_EVSYNCRATE
4Ch	PEROPRATE	Peripheral Operational Rate	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PEROPRATE
50h	ADCCLKCTL	ADC Clock Control	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_ADCCLKCTL
54h	TDCCLKCTL	TDC Counter Clock Control	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TDCCLKCTL
58h	TDCREFCLKCTL	TDC Reference Clock Control	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TDCREFCLKCTL
5Ch	TIMER2CLKCTL	AUX_TIMER2 Clock Control	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2CLKCTL
60h	TIMER2CLKSTAT	AUX_TIMER2 Clock Status	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2CLKSTAT
64h	TIMER2CLKSWITCH	AUX_TIMER2 Clock Switch	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2CLKSWITCH
68h	TIMER2DBGCTL	AUX_TIMER2 Debug Control	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2DBGCTL
70h	CLKSHIFTDET	Clock Shift Detection	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_CLKSHIFTDET
74h	RECHARGETRIG	VDDR Recharge Trigger	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RECHARGETRIG
78h	RECHARGEDET	VDDR Recharge Detection	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RECHARGEDET
7Ch	RTCSUBSECINC0	Real Time Counter Sub Second Increment 0	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSECINC0
80h	RTCSUBSECINC1	Real Time Counter Sub Second Increment 1	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSECINC1
84h	RTCSUBSECINCCTL	Real Time Counter Sub Second Increment Control	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSECINCCTL
88h	RTCSEC	Real Time Counter Second	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSEC
8Ch	RTCSUBSEC	Real Time Counter Sub-Second	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSEC
90h	RTCEVCLR	AON_RTC Event Clear	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCEVCLR
94h	BATMONBAT	AON_BATMON Battery Voltage Value	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_BATMONBAT
9Ch	BATMONTEMP	AON_BATMON Temperature Value	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_BATMONTEMP
A0h	TIMERHALT	Timer Halt	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMERHALT
B0h	TIMER2BRIDGE	AUX_TIMER2 Bridge	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2BRIDGE
B4h	SWPWRPROF	Software Power Profiler	#AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_SWPWRPROF

Complex bit access types are encoded to fit into small table cells. #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_LEGEND shows the codes that are used for access types in this section.

Table 20-175 AUX_SYSIF Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

20.8.9.1 OPMODEREQ Register (Offset = 0h) [Reset = 00000000h]

OPMODEREQ is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_OPMODEREQ_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_OPMODEREQ_TABLE.

Return to the Summary Table.

Operational Mode Request
AUX can operate in three operational modes. Each mode is associated with:
- a SCE clock source or rate, given by AON_PMCTL:AUXSCECLK. This rate is termed SCE_RATE.
- a system power supply state request. AUX can request powerdown (uLDO) or active (GLDO or DCDC) system power supply state.
- a specific system response to an active AUX wakeup flag. The response is dependent on what operational mode is requested.
uLDO power supply state offers limited current supply. AUX_SCE cannot use certain peripherals and functions such as AUX_DDI0_OSC, AUX_TDC and AUX_ANAIF ADC interface in this power supply state.
Follow these rules:
- It is not allowed to change a request until it has been acknowledged through OPMODEACK.
- A change in mode request must happen stepwise along this sequence, the direction is irrelevant:
PDA - A - LP - PDLP.
Failure to follow these rules might result in unexpected behavior and must be avoided.

Figure 20-154 OPMODEREQ Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														REQ
R-0h														R/W-0h

Table 20-176 OPMODEREQ Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

Reserved

1-0

REQ

R/W

AUX operational mode request.

0h = Active operational mode, characterized by:
- Active system power supply state (GLDO or DCDC) request.
- AON_PMCTL:AUXSCECLK.SRC sets the SCE clock frequency (SCE_RATE).
- An active wakeup flag does not change operational mode.

1h = Lowpower operational mode, characterized by:
- Powerdown system power supply state (uLDO) request.
- SCE clock frequency (SCE_RATE) equals SCLK_MF.
- An active wakeup flag does not change operational mode.

2h = Powerdown operational mode with wakeup to active mode, characterized by:
- Powerdown system power supply state (uLDO) request.
- AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock frequency (SCE_RATE).
- An active wakeup flag overrides the operational mode externally to active (A) as long as the flag is set.

3h = Powerdown operational mode with wakeup to lowpower mode, characterized by:
- Powerdown system power supply state (uLDO) request.
- AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock frequency (SCE_RATE).
- An active wakeup flag overrides the operational mode externally to lowpower (LP) as long as the flag is set.

20.8.9.2 OPMODEACK Register (Offset = 4h) [Reset = 00000000h]

OPMODEACK is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_OPMODEACK_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_OPMODEACK_TABLE.

Return to the Summary Table.

Operational Mode Acknowledgement
AUX_SCE program must assume that the current operational mode is the one acknowledged.

Figure 20-155 OPMODEACK Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														ACK
R-0h														R-0h

Table 20-177 OPMODEACK Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

Reserved

1-0

ACK

AUX operational mode acknowledgement.

0h = Active operational mode is acknowledged.

1h = Lowpower operational mode is acknowledged.

2h = Powerdown operational mode with wakeup to active mode is acknowledged.

3h = Powerdown operational mode with wakeup to lowpower mode is acknowledged.

20.8.9.3 PROGWU0CFG Register (Offset = 8h) [Reset = 00000000h]

PROGWU0CFG is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU0CFG_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU0CFG_TABLE.

Return to the Summary Table.

Programmable Wakeup 0 Configuration
Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU0 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

Figure 20-156 PROGWU0CFG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								POL	EN	WU_SRC
R-0h								R/W-0h	R/W-0h	R/W-0h

Table 20-178 PROGWU0CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	POL	R/W	0h	Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU0. 0h = The wakeup flag is set when WU_SRC is high or goes high. 1h = The wakeup flag is set when WU_SRC is low or goes low.
6	EN	R/W	0h	Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag.
5-0	WU_SRC	R/W	0h	Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 0h = AUX_EVCTL:EVSTAT0.AUXIO0 1h = AUX_EVCTL:EVSTAT0.AUXIO1 2h = AUX_EVCTL:EVSTAT0.AUXIO2 3h = AUX_EVCTL:EVSTAT0.AUXIO3 4h = AUX_EVCTL:EVSTAT0.AUXIO4 5h = AUX_EVCTL:EVSTAT0.AUXIO5 6h = AUX_EVCTL:EVSTAT0.AUXIO6 7h = AUX_EVCTL:EVSTAT0.AUXIO7 8h = AUX_EVCTL:EVSTAT0.AUXIO8 9h = AUX_EVCTL:EVSTAT0.AUXIO9 Ah = AUX_EVCTL:EVSTAT0.AUXIO10 Bh = AUX_EVCTL:EVSTAT0.AUXIO11 Ch = AUX_EVCTL:EVSTAT0.AUXIO12 Dh = AUX_EVCTL:EVSTAT0.AUXIO13 Eh = AUX_EVCTL:EVSTAT0.AUXIO14 Fh = AUX_EVCTL:EVSTAT0.AUXIO15 10h = AUX_EVCTL:EVSTAT1.AUXIO16 11h = AUX_EVCTL:EVSTAT1.AUXIO17 12h = AUX_EVCTL:EVSTAT1.AUXIO18 13h = AUX_EVCTL:EVSTAT1.AUXIO19 14h = AUX_EVCTL:EVSTAT1.AUXIO20 15h = AUX_EVCTL:EVSTAT1.AUXIO21 16h = AUX_EVCTL:EVSTAT1.AUXIO22 17h = AUX_EVCTL:EVSTAT1.AUXIO23 18h = AUX_EVCTL:EVSTAT1.AUXIO24 19h = AUX_EVCTL:EVSTAT1.AUXIO25 1Ah = AUX_EVCTL:EVSTAT1.AUXIO26 1Bh = AUX_EVCTL:EVSTAT1.AUXIO27 1Ch = AUX_EVCTL:EVSTAT1.AUXIO28 1Dh = AUX_EVCTL:EVSTAT1.AUXIO29 1Eh = AUX_EVCTL:EVSTAT1.AUXIO30 1Fh = AUX_EVCTL:EVSTAT1.AUXIO31 20h = AUX_EVCTL:EVSTAT2.MANUAL_EV 21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2 22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 26h = AUX_EVCTL:EVSTAT2.SCLK_LF 27h = AUX_EVCTL:EVSTAT2.PWR_DWN 28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE 29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF 2Bh = AUX_EVCTL:EVSTAT2.MCU_EV 2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA 2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB 30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Fh = No event.

20.8.9.4 PROGWU1CFG Register (Offset = Ch) [Reset = 00000000h]

PROGWU1CFG is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU1CFG_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU1CFG_TABLE.

Return to the Summary Table.

Programmable Wakeup 1 Configuration
Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU1 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

Figure 20-157 PROGWU1CFG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								POL	EN	WU_SRC
R-0h								R/W-0h	R/W-0h	R/W-0h

Table 20-179 PROGWU1CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	POL	R/W	0h	Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU1. 0h = The wakeup flag is set when WU_SRC is high or goes high. 1h = The wakeup flag is set when WU_SRC is low or goes low.
6	EN	R/W	0h	Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag.
5-0	WU_SRC	R/W	0h	Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 0h = AUX_EVCTL:EVSTAT0.AUXIO0 1h = AUX_EVCTL:EVSTAT0.AUXIO1 2h = AUX_EVCTL:EVSTAT0.AUXIO2 3h = AUX_EVCTL:EVSTAT0.AUXIO3 4h = AUX_EVCTL:EVSTAT0.AUXIO4 5h = AUX_EVCTL:EVSTAT0.AUXIO5 6h = AUX_EVCTL:EVSTAT0.AUXIO6 7h = AUX_EVCTL:EVSTAT0.AUXIO7 8h = AUX_EVCTL:EVSTAT0.AUXIO8 9h = AUX_EVCTL:EVSTAT0.AUXIO9 Ah = AUX_EVCTL:EVSTAT0.AUXIO10 Bh = AUX_EVCTL:EVSTAT0.AUXIO11 Ch = AUX_EVCTL:EVSTAT0.AUXIO12 Dh = AUX_EVCTL:EVSTAT0.AUXIO13 Eh = AUX_EVCTL:EVSTAT0.AUXIO14 Fh = AUX_EVCTL:EVSTAT0.AUXIO15 10h = AUX_EVCTL:EVSTAT1.AUXIO16 11h = AUX_EVCTL:EVSTAT1.AUXIO17 12h = AUX_EVCTL:EVSTAT1.AUXIO18 13h = AUX_EVCTL:EVSTAT1.AUXIO19 14h = AUX_EVCTL:EVSTAT1.AUXIO20 15h = AUX_EVCTL:EVSTAT1.AUXIO21 16h = AUX_EVCTL:EVSTAT1.AUXIO22 17h = AUX_EVCTL:EVSTAT1.AUXIO23 18h = AUX_EVCTL:EVSTAT1.AUXIO24 19h = AUX_EVCTL:EVSTAT1.AUXIO25 1Ah = AUX_EVCTL:EVSTAT1.AUXIO26 1Bh = AUX_EVCTL:EVSTAT1.AUXIO27 1Ch = AUX_EVCTL:EVSTAT1.AUXIO28 1Dh = AUX_EVCTL:EVSTAT1.AUXIO29 1Eh = AUX_EVCTL:EVSTAT1.AUXIO30 1Fh = AUX_EVCTL:EVSTAT1.AUXIO31 20h = AUX_EVCTL:EVSTAT2.MANUAL_EV 21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2 22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 26h = AUX_EVCTL:EVSTAT2.SCLK_LF 27h = AUX_EVCTL:EVSTAT2.PWR_DWN 28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE 29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF 2Bh = AUX_EVCTL:EVSTAT2.MCU_EV 2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA 2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB 30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Fh = No event.

20.8.9.5 PROGWU2CFG Register (Offset = 10h) [Reset = 00000000h]

PROGWU2CFG is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU2CFG_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU2CFG_TABLE.

Return to the Summary Table.

Programmable Wakeup 2 Configuration
Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU2 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

Figure 20-158 PROGWU2CFG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								POL	EN	WU_SRC
R-0h								R/W-0h	R/W-0h	R/W-0h

Table 20-180 PROGWU2CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	POL	R/W	0h	Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU2. 0h = The wakeup flag is set when WU_SRC is high or goes high. 1h = The wakeup flag is set when WU_SRC is low or goes low.
6	EN	R/W	0h	Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag.
5-0	WU_SRC	R/W	0h	Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 0h = AUX_EVCTL:EVSTAT0.AUXIO0 1h = AUX_EVCTL:EVSTAT0.AUXIO1 2h = AUX_EVCTL:EVSTAT0.AUXIO2 3h = AUX_EVCTL:EVSTAT0.AUXIO3 4h = AUX_EVCTL:EVSTAT0.AUXIO4 5h = AUX_EVCTL:EVSTAT0.AUXIO5 6h = AUX_EVCTL:EVSTAT0.AUXIO6 7h = AUX_EVCTL:EVSTAT0.AUXIO7 8h = AUX_EVCTL:EVSTAT0.AUXIO8 9h = AUX_EVCTL:EVSTAT0.AUXIO9 Ah = AUX_EVCTL:EVSTAT0.AUXIO10 Bh = AUX_EVCTL:EVSTAT0.AUXIO11 Ch = AUX_EVCTL:EVSTAT0.AUXIO12 Dh = AUX_EVCTL:EVSTAT0.AUXIO13 Eh = AUX_EVCTL:EVSTAT0.AUXIO14 Fh = AUX_EVCTL:EVSTAT0.AUXIO15 10h = AUX_EVCTL:EVSTAT1.AUXIO16 11h = AUX_EVCTL:EVSTAT1.AUXIO17 12h = AUX_EVCTL:EVSTAT1.AUXIO18 13h = AUX_EVCTL:EVSTAT1.AUXIO19 14h = AUX_EVCTL:EVSTAT1.AUXIO20 15h = AUX_EVCTL:EVSTAT1.AUXIO21 16h = AUX_EVCTL:EVSTAT1.AUXIO22 17h = AUX_EVCTL:EVSTAT1.AUXIO23 18h = AUX_EVCTL:EVSTAT1.AUXIO24 19h = AUX_EVCTL:EVSTAT1.AUXIO25 1Ah = AUX_EVCTL:EVSTAT1.AUXIO26 1Bh = AUX_EVCTL:EVSTAT1.AUXIO27 1Ch = AUX_EVCTL:EVSTAT1.AUXIO28 1Dh = AUX_EVCTL:EVSTAT1.AUXIO29 1Eh = AUX_EVCTL:EVSTAT1.AUXIO30 1Fh = AUX_EVCTL:EVSTAT1.AUXIO31 20h = AUX_EVCTL:EVSTAT2.MANUAL_EV 21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2 22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 26h = AUX_EVCTL:EVSTAT2.SCLK_LF 27h = AUX_EVCTL:EVSTAT2.PWR_DWN 28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE 29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF 2Bh = AUX_EVCTL:EVSTAT2.MCU_EV 2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA 2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB 30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Fh = No event.

20.8.9.6 PROGWU3CFG Register (Offset = 14h) [Reset = 00000000h]

PROGWU3CFG is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU3CFG_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PROGWU3CFG_TABLE.

Return to the Summary Table.

Programmable Wakeup 3 Configuration
Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU3 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

Figure 20-159 PROGWU3CFG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								POL	EN	WU_SRC
R-0h								R/W-0h	R/W-0h	R/W-0h

Table 20-181 PROGWU3CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	POL	R/W	0h	Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU3. 0h = The wakeup flag is set when WU_SRC is high or goes high. 1h = The wakeup flag is set when WU_SRC is low or goes low.
6	EN	R/W	0h	Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag.
5-0	WU_SRC	R/W	0h	Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 0h = AUX_EVCTL:EVSTAT0.AUXIO0 1h = AUX_EVCTL:EVSTAT0.AUXIO1 2h = AUX_EVCTL:EVSTAT0.AUXIO2 3h = AUX_EVCTL:EVSTAT0.AUXIO3 4h = AUX_EVCTL:EVSTAT0.AUXIO4 5h = AUX_EVCTL:EVSTAT0.AUXIO5 6h = AUX_EVCTL:EVSTAT0.AUXIO6 7h = AUX_EVCTL:EVSTAT0.AUXIO7 8h = AUX_EVCTL:EVSTAT0.AUXIO8 9h = AUX_EVCTL:EVSTAT0.AUXIO9 Ah = AUX_EVCTL:EVSTAT0.AUXIO10 Bh = AUX_EVCTL:EVSTAT0.AUXIO11 Ch = AUX_EVCTL:EVSTAT0.AUXIO12 Dh = AUX_EVCTL:EVSTAT0.AUXIO13 Eh = AUX_EVCTL:EVSTAT0.AUXIO14 Fh = AUX_EVCTL:EVSTAT0.AUXIO15 10h = AUX_EVCTL:EVSTAT1.AUXIO16 11h = AUX_EVCTL:EVSTAT1.AUXIO17 12h = AUX_EVCTL:EVSTAT1.AUXIO18 13h = AUX_EVCTL:EVSTAT1.AUXIO19 14h = AUX_EVCTL:EVSTAT1.AUXIO20 15h = AUX_EVCTL:EVSTAT1.AUXIO21 16h = AUX_EVCTL:EVSTAT1.AUXIO22 17h = AUX_EVCTL:EVSTAT1.AUXIO23 18h = AUX_EVCTL:EVSTAT1.AUXIO24 19h = AUX_EVCTL:EVSTAT1.AUXIO25 1Ah = AUX_EVCTL:EVSTAT1.AUXIO26 1Bh = AUX_EVCTL:EVSTAT1.AUXIO27 1Ch = AUX_EVCTL:EVSTAT1.AUXIO28 1Dh = AUX_EVCTL:EVSTAT1.AUXIO29 1Eh = AUX_EVCTL:EVSTAT1.AUXIO30 1Fh = AUX_EVCTL:EVSTAT1.AUXIO31 20h = AUX_EVCTL:EVSTAT2.MANUAL_EV 21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2 22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 26h = AUX_EVCTL:EVSTAT2.SCLK_LF 27h = AUX_EVCTL:EVSTAT2.PWR_DWN 28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE 29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF 2Bh = AUX_EVCTL:EVSTAT2.MCU_EV 2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA 2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB 30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Fh = No event.

20.8.9.7 SWWUTRIG Register (Offset = 18h) [Reset = 00000000h]

SWWUTRIG is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_SWWUTRIG_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_SWWUTRIG_TABLE.

Return to the Summary Table.

Software Wakeup Triggers
System CPU uses these wakeup flags to perform handshaking with AUX_SCE. The wakeup flags can change the operational mode of AUX and guarantees a non-zero SCE clock rate. AUX_SCE wakeup vectors are configured in VECCFGn.

Figure 20-160 SWWUTRIG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				SW_WU3	SW_WU2	SW_WU1	SW_WU0
R-0h				W-0h	W-0h	W-0h	W-0h

Table 20-182 SWWUTRIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	SW_WU3	W	0h	Software wakeup 3 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup.
2	SW_WU2	W	0h	Software wakeup 2 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup.
1	SW_WU1	W	0h	Software wakeup 1 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup.
0	SW_WU0	W	0h	Software wakeup 0 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup.

20.8.9.8 WUFLAGS Register (Offset = 1Ch) [Reset = 00000000h]

WUFLAGS is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_WUFLAGS_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_WUFLAGS_TABLE.

Return to the Summary Table.

Wakeup Flags
This register holds the eight AUX wakeup flags. Each flag can cause AUX operational mode to change as given in OPMODEREQ. To clear flag n you must set bit n in WUFLAGSCLR until flag n is read as 0. You must clear bit n in WUFLAGSCLR before flag n can be set again.

Figure 20-161 WUFLAGS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
SW_WU3	SW_WU2	SW_WU1	SW_WU0	PROG_WU3	PROG_WU2	PROG_WU1	PROG_WU0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 20-183 WUFLAGS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	SW_WU3	R	0h	Software wakeup 3 flag. 0: Software wakeup 3 not triggered. 1: Software wakeup 3 triggered.
6	SW_WU2	R	0h	Software wakeup 2 flag. 0: Software wakeup 2 not triggered. 1: Software wakeup 2 triggered.
5	SW_WU1	R	0h	Software wakeup 1 flag. 0: Software wakeup 1 not triggered. 1: Software wakeup 1 triggered.
4	SW_WU0	R	0h	Software wakeup 0 flag. 0: Software wakeup 0 not triggered. 1: Software wakeup 0 triggered.
3	PROG_WU3	R	0h	Programmable wakeup 3. 0: Programmable wakeup 3 not triggered. 1: Programmable wakeup 3 triggered.
2	PROG_WU2	R	0h	Programmable wakeup 2. 0: Programmable wakeup 2 not triggered. 1: Programmable wakeup 2 triggered.
1	PROG_WU1	R	0h	Programmable wakeup 1. 0: Programmable wakeup 1 not triggered. 1: Programmable wakeup 1 triggered.
0	PROG_WU0	R	0h	Programmable wakeup 0. 0: Programmable wakeup 0 not triggered. 1: Programmable wakeup 0 triggered.

20.8.9.9 WUFLAGSCLR Register (Offset = 20h) [Reset = 0000000Fh]

WUFLAGSCLR is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_WUFLAGSCLR_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_WUFLAGSCLR_TABLE.

Return to the Summary Table.

Wakeup Flags Clear
This register clears AUX wakeup flags WUFLAGS.
To clear programmable wakeup flags you must disable the AUX wakeup output first. After the programmable wakeup flags are cleared you must re-enable the AUX wakeup output. Write WUGATE to disable or enable the AUX wakeup output. This procedure is not required when you want to clear a software-triggered wakeup.

Figure 20-162 WUFLAGSCLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
SW_WU3	SW_WU2	SW_WU1	SW_WU0	PROG_WU3	PROG_WU2	PROG_WU1	PROG_WU0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-1h	R/W-1h	R/W-1h	R/W-1h

Table 20-184 WUFLAGSCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	SW_WU3	R/W	0h	Clear software wakeup flag 3. 0: No effect. 1: Clear WUFLAGS.SW_WU3. Keep high until WUFLAGS.SW_WU3 is 0.
6	SW_WU2	R/W	0h	Clear software wakeup flag 2. 0: No effect. 1: Clear WUFLAGS.SW_WU2. Keep high until WUFLAGS.SW_WU2 is 0.
5	SW_WU1	R/W	0h	Clear software wakeup flag 1. 0: No effect. 1: Clear WUFLAGS.SW_WU1. Keep high until WUFLAGS.SW_WU1 is 0.
4	SW_WU0	R/W	0h	Clear software wakeup flag 0. 0: No effect. 1: Clear WUFLAGS.SW_WU0. Keep high until WUFLAGS.SW_WU0 is 0.
3	PROG_WU3	R/W	1h	Programmable wakeup flag 3. 0: No effect. 1: Clear WUFLAGS.PROG_WU3. Keep high until WUFLAGS.PROG_WU3 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU3 to 0 when PROGWU3CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU3 to 0 when PROGWU3CFG.EN is 0, then set PROGWU3CFG.EN.
2	PROG_WU2	R/W	1h	Programmable wakeup flag 2. 0: No effect. 1: Clear WUFLAGS.PROG_WU2. Keep high until WUFLAGS.PROG_WU2 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU2 to 0 when PROGWU2CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU2 to 0 when PROGWU2CFG.EN is 0, then set PROGWU2CFG.EN.
1	PROG_WU1	R/W	1h	Programmable wakeup flag 1. 0: No effect. 1: Clear WUFLAGS.PROG_WU1. Keep high until WUFLAGS.PROG_WU1 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU1 to 0 when PROGWU1CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU1 to 0 when PROGWU1CFG.EN is 0, then set PROGWU1CFG.EN.
0	PROG_WU0	R/W	1h	Programmable wakeup flag 0. 0: No effect. 1: Clear WUFLAGS.PROG_WU0. Keep high until WUFLAGS.PROG_WU0 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU0 to 0 when PROGWU0CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU0 to 0 when PROGWU0CFG.EN is 0, then set PROGWU0CFG.EN.

20.8.9.10 WUGATE Register (Offset = 24h) [Reset = 00000000h]

WUGATE is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_WUGATE_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_WUGATE_TABLE.

Return to the Summary Table.

Wakeup Gate
You must disable the AUX wakeup output:
- Before you clear a programmable wakeup flag.
- Before you change the value of [PROGWUnCFG.EN] or [PROGWUnCFG.WU_SRC].
The AUX wakeup output must be re-enabled after clear operation or programmable wakeup configuration.

Figure 20-163 WUGATE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															EN
R-0h															R/W-0h

Table 20-185 WUGATE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EN	R/W	0h	Wakeup output enable. 0: Disable AUX wakeup output. 1: Enable AUX wakeup output.

20.8.9.11 VECCFG0 Register (Offset = 28h) [Reset = 00000000h]

VECCFG0 is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG0_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG0_TABLE.

Return to the Summary Table.

Vector Configuration 0
AUX_SCE wakeup vector 0 configuration

Figure 20-164 VECCFG0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												VEC_EV
R-0h												R/W-0h

Table 20-186 VECCFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

VEC_EV

R/W

Select trigger event for vector 0.
Non-enumerated values are treated as NONE.

0h = Vector is disabled.

1h = WUFLAGS.PROG_WU0

2h = WUFLAGS.PROG_WU1

3h = WUFLAGS.PROG_WU2

4h = WUFLAGS.PROG_WU3

5h = WUFLAGS.SW_WU0

6h = WUFLAGS.SW_WU1

7h = WUFLAGS.SW_WU2

8h = WUFLAGS.SW_WU3

9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.12 VECCFG1 Register (Offset = 2Ch) [Reset = 00000000h]

VECCFG1 is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG1_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG1_TABLE.

Return to the Summary Table.

Vector Configuration 1
AUX_SCE wakeup vector 1 configuration

Figure 20-165 VECCFG1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												VEC_EV
R-0h												R/W-0h

Table 20-187 VECCFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

VEC_EV

R/W

Select trigger event for vector 1.
Non-enumerated values are treated as NONE.

0h = Vector is disabled.

1h = WUFLAGS.PROG_WU0

2h = WUFLAGS.PROG_WU1

3h = WUFLAGS.PROG_WU2

4h = WUFLAGS.PROG_WU3

5h = WUFLAGS.SW_WU0

6h = WUFLAGS.SW_WU1

7h = WUFLAGS.SW_WU2

8h = WUFLAGS.SW_WU3

9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.13 VECCFG2 Register (Offset = 30h) [Reset = 00000000h]

VECCFG2 is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG2_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG2_TABLE.

Return to the Summary Table.

Vector Configuration 2
AUX_SCE wakeup vector 2 configuration

Figure 20-166 VECCFG2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												VEC_EV
R-0h												R/W-0h

Table 20-188 VECCFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

VEC_EV

R/W

Select trigger event for vector 2.
Non-enumerated values are treated as NONE.

0h = Vector is disabled.

1h = WUFLAGS.PROG_WU0

2h = WUFLAGS.PROG_WU1

3h = WUFLAGS.PROG_WU2

4h = WUFLAGS.PROG_WU3

5h = WUFLAGS.SW_WU0

6h = WUFLAGS.SW_WU1

7h = WUFLAGS.SW_WU2

8h = WUFLAGS.SW_WU3

9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.14 VECCFG3 Register (Offset = 34h) [Reset = 00000000h]

VECCFG3 is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG3_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG3_TABLE.

Return to the Summary Table.

Vector Configuration 3
AUX_SCE wakeup vector 3 configuration

Figure 20-167 VECCFG3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												VEC_EV
R-0h												R/W-0h

Table 20-189 VECCFG3 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

VEC_EV

R/W

Select trigger event for vector 3.
Non-enumerated values are treated as NONE.

0h = Vector is disabled.

1h = WUFLAGS.PROG_WU0

2h = WUFLAGS.PROG_WU1

3h = WUFLAGS.PROG_WU2

4h = WUFLAGS.PROG_WU3

5h = WUFLAGS.SW_WU0

6h = WUFLAGS.SW_WU1

7h = WUFLAGS.SW_WU2

8h = WUFLAGS.SW_WU3

9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.15 VECCFG4 Register (Offset = 38h) [Reset = 00000000h]

VECCFG4 is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG4_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG4_TABLE.

Return to the Summary Table.

Vector Configuration 4
AUX_SCE wakeup vector 4 configuration

Figure 20-168 VECCFG4 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												VEC_EV
R-0h												R/W-0h

Table 20-190 VECCFG4 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

VEC_EV

R/W

Select trigger event for vector 4.
Non-enumerated values are treated as NONE.

0h = Vector is disabled.

1h = WUFLAGS.PROG_WU0

2h = WUFLAGS.PROG_WU1

3h = WUFLAGS.PROG_WU2

4h = WUFLAGS.PROG_WU3

5h = WUFLAGS.SW_WU0

6h = WUFLAGS.SW_WU1

7h = WUFLAGS.SW_WU2

8h = WUFLAGS.SW_WU3

9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.16 VECCFG5 Register (Offset = 3Ch) [Reset = 00000000h]

VECCFG5 is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG5_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG5_TABLE.

Return to the Summary Table.

Vector Configuration 5
AUX_SCE wakeup vector 5 configuration

Figure 20-169 VECCFG5 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												VEC_EV
R-0h												R/W-0h

Table 20-191 VECCFG5 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

VEC_EV

R/W

Select trigger event for vector 5.
Non-enumerated values are treated as NONE.

0h = Vector is disabled.

1h = WUFLAGS.PROG_WU0

2h = WUFLAGS.PROG_WU1

3h = WUFLAGS.PROG_WU2

4h = WUFLAGS.PROG_WU3

5h = WUFLAGS.SW_WU0

6h = WUFLAGS.SW_WU1

7h = WUFLAGS.SW_WU2

8h = WUFLAGS.SW_WU3

9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.17 VECCFG6 Register (Offset = 40h) [Reset = 00000000h]

VECCFG6 is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG6_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG6_TABLE.

Return to the Summary Table.

Vector Configuration 6
AUX_SCE wakeup vector 6 configuration

Figure 20-170 VECCFG6 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												VEC_EV
R-0h												R/W-0h

Table 20-192 VECCFG6 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

VEC_EV

R/W

Select trigger event for vector 6.
Non-enumerated values are treated as NONE.

0h = Vector is disabled.

1h = WUFLAGS.PROG_WU0

2h = WUFLAGS.PROG_WU1

3h = WUFLAGS.PROG_WU2

4h = WUFLAGS.PROG_WU3

5h = WUFLAGS.SW_WU0

6h = WUFLAGS.SW_WU1

7h = WUFLAGS.SW_WU2

8h = WUFLAGS.SW_WU3

9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.18 VECCFG7 Register (Offset = 44h) [Reset = 00000000h]

VECCFG7 is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG7_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_VECCFG7_TABLE.

Return to the Summary Table.

Vector Configuration 7
AUX_SCE wakeup vector 7 configuration

Figure 20-171 VECCFG7 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												VEC_EV
R-0h												R/W-0h

Table 20-193 VECCFG7 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

VEC_EV

R/W

Select trigger event for vector 7.
Non-enumerated values are treated as NONE.

0h = Vector is disabled.

1h = WUFLAGS.PROG_WU0

2h = WUFLAGS.PROG_WU1

3h = WUFLAGS.PROG_WU2

4h = WUFLAGS.PROG_WU3

5h = WUFLAGS.SW_WU0

6h = WUFLAGS.SW_WU1

7h = WUFLAGS.SW_WU2

8h = WUFLAGS.SW_WU3

9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.19 EVSYNCRATE Register (Offset = 48h) [Reset = 00000000h]

EVSYNCRATE is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_EVSYNCRATE_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_EVSYNCRATE_TABLE.

Return to the Summary Table.

Event Synchronization Rate
Configure synchronization rate for certain events to the synchronous AUX event bus.
You must select SCE rate when AUX_SCE uses the event. You must select AUX bus rate when system CPU uses the event.
SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by two when MCU domain is active.

Figure 20-172 EVSYNCRATE Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					AUX_COMPA_SYNC_RATE	AUX_COMPB_SYNC_RATE	AUX_TIMER2_SYNC_RATE
R-0h					R/W-0h	R/W-0h	R/W-0h

Table 20-194 EVSYNCRATE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	AUX_COMPA_SYNC_RATE	R/W	0h	Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event. 0h = SCE rate 1h = AUX bus rate
1	AUX_COMPB_SYNC_RATE	R/W	0h	Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event. 0h = SCE rate 1h = AUX bus rate
0	AUX_TIMER2_SYNC_RATE	R/W	0h	Select synchronization rate for: - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 0h = SCE rate 1h = AUX bus rate

20.8.9.20 PEROPRATE Register (Offset = 4Ch) [Reset = 00000000h]

PEROPRATE is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PEROPRATE_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_PEROPRATE_TABLE.

Return to the Summary Table.

Peripheral Operational Rate
Some AUX peripherals are operated at either SCE or at AUX bus rate.
You must select SCE rate when AUX_SCE uses such peripheral or an event produced by it. You must select AUX bus rate when system CPU uses such peripheral.
SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by 2 when MCU domain is active.

Figure 20-173 PEROPRATE Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				ANAIF_DAC_OP_RATE	TIMER01_OP_RATE	SPIM_OP_RATE	MAC_OP_RATE
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 20-195 PEROPRATE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	ANAIF_DAC_OP_RATE	R/W	0h	Select operational rate for AUX_ANAIF DAC sample clock state machine. 0h = SCE rate 1h = AUX bus rate
2	TIMER01_OP_RATE	R/W	0h	Select operational rate for AUX_TIMER01. 0h = SCE rate 1h = AUX bus rate
1	SPIM_OP_RATE	R/W	0h	Select operational rate for AUX_SPIM. 0h = SCE rate 1h = AUX bus rate
0	MAC_OP_RATE	R/W	0h	Select operational rate for AUX_MAC. 0h = SCE rate 1h = AUX bus rate

20.8.9.21 ADCCLKCTL Register (Offset = 50h) [Reset = 00000000h]

ADCCLKCTL is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_ADCCLKCTL_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_ADCCLKCTL_TABLE.

Return to the Summary Table.

ADC Clock Control

Figure 20-174 ADCCLKCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														ACK	REQ
R-0h														R-0h	R/W-0h

Table 20-196 ADCCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	ACK	R	0h	Clock acknowledgement. 0: ADC clock is disabled. 1: ADC clock is enabled.
0	REQ	R/W	0h	ADC clock request. 0: Disable ADC clock. 1: Enable ADC clock. Only modify REQ when equal to ACK.

20.8.9.22 TDCCLKCTL Register (Offset = 54h) [Reset = 00000000h]

TDCCLKCTL is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TDCCLKCTL_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TDCCLKCTL_TABLE.

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TDC Counter Clock Control
Controls if the AUX_TDC counter clock source is enabled. TDC counter clock source is configured in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL.

Figure 20-175 TDCCLKCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														ACK	REQ
R-0h														R-0h	R/W-0h

Table 20-197 TDCCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1	ACK	R	0h	TDC counter clock acknowledgement. 0: TDC counter clock is disabled. 1: TDC counter clock is enabled.
0	REQ	R/W	0h	TDC counter clock request. 0: Disable TDC counter clock. 1: Enable TDC counter clock. Only modify REQ when equal to ACK.

20.8.9.23 TDCREFCLKCTL Register (Offset = 58h) [Reset = 00000000h]

TDCREFCLKCTL is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TDCREFCLKCTL_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TDCREFCLKCTL_TABLE.

Return to the Summary Table.

TDC Reference Clock Control
Controls if the AUX_TDC reference clock source is enabled. This clock is compared against the AUX_TDC counter clock. TDC reference clock source is configured in DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL.

Figure 20-176 TDCREFCLKCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														ACK	REQ
R-0h														R-0h	R/W-0h

Table 20-198 TDCREFCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	ACK	R	0h	TDC reference clock acknowledgement. 0: TDC reference clock is disabled. 1: TDC reference clock is enabled.
0	REQ	R/W	0h	TDC reference clock request. 0: Disable TDC reference clock. 1: Enable TDC reference clock. Only modify REQ when equal to ACK.

20.8.9.24 TIMER2CLKCTL Register (Offset = 5Ch) [Reset = 00000000h]

TIMER2CLKCTL is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2CLKCTL_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2CLKCTL_TABLE.

Return to the Summary Table.

AUX_TIMER2 Clock Control
Access to AUX_TIMER2 is only possible when TIMER2CLKSTAT.STAT is different from NONE.

Figure 20-177 TIMER2CLKCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																													SRC
R-0h																													R/W-0h

Table 20-199 TIMER2CLKCTL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

Reserved

2-0

SRC

R/W

Select clock source for AUX_TIMER2.
Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or TIMER2CLKSWITCH.RDY is 1.
It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0.
A non-enumerated value is ignored.

0h = no clock

1h = SCLK_LF

2h = SCLK_MF

4h = SCLK_HF / 2

20.8.9.25 TIMER2CLKSTAT Register (Offset = 60h) [Reset = 00000000h]

TIMER2CLKSTAT is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2CLKSTAT_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2CLKSTAT_TABLE.

Return to the Summary Table.

AUX_TIMER2 Clock Status

Figure 20-178 TIMER2CLKSTAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													STAT
R-0h													R-0h

Table 20-200 TIMER2CLKSTAT Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

Reserved

2-0

STAT

AUX_TIMER2 clock source status.

0h = No clock

1h = SCLK_LF

2h = SCLK_MF

4h = SCLK_HF / 2

20.8.9.26 TIMER2CLKSWITCH Register (Offset = 64h) [Reset = 00000001h]

TIMER2CLKSWITCH is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2CLKSWITCH_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2CLKSWITCH_TABLE.

Return to the Summary Table.

AUX_TIMER2 Clock Switch

Figure 20-179 TIMER2CLKSWITCH Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															RDY
R-0h															R-1h

Table 20-201 TIMER2CLKSWITCH Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	RDY	R	1h	Status of clock switcher. 0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT. 1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT. RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY.

20.8.9.27 TIMER2DBGCTL Register (Offset = 68h) [Reset = 00000000h]

TIMER2DBGCTL is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2DBGCTL_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2DBGCTL_TABLE.

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AUX_TIMER2 Debug Control

Figure 20-180 TIMER2DBGCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							DBG_FREEZE_EN
R-0h							R/W-0h

Table 20-202 TIMER2DBGCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	DBG_FREEZE_EN	R/W	0h	Debug freeze enable. 0: AUX_TIMER2 does not halt when the system CPU halts in debug mode. 1: Halt AUX_TIMER2 when the system CPU halts in debug mode.

20.8.9.28 CLKSHIFTDET Register (Offset = 70h) [Reset = 00000001h]

CLKSHIFTDET is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_CLKSHIFTDET_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_CLKSHIFTDET_TABLE.

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Clock Shift Detection
A transition in the MCU domain state causes a non-accumulative change to the SCE clock period when the AUX clock rate is derived from SCLK_MF or SCLK_LF:
- A single SCE clock cycle is 6 thru 8 SCLK_HF cycles longer when MCU domain enters active state.
- A single SCE clock cycle is 6 thru 8 SCLK_HF cycles shorter when MCU domain exits active state.

AUX_SCE detects if such events occurred to the SCE clock during the time period between a clear of STAT and a read of STAT.

Figure 20-181 CLKSHIFTDET Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							STAT
R-0h							R/W-1h

Table 20-203 CLKSHIFTDET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	STAT	R/W	1h	Clock shift detection. Write: 0: Restart clock shift detection. 1: Do not use. Read: 0: MCU domain did not enter or exit active state since you wrote 0 to STAT. 1: MCU domain entered or exited active state since you wrote 0 to STAT.

20.8.9.29 RECHARGETRIG Register (Offset = 74h) [Reset = 00000000h]

RECHARGETRIG is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RECHARGETRIG_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RECHARGETRIG_TABLE.

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VDDR Recharge Trigger

Figure 20-182 RECHARGETRIG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							TRIG
R-0h							R/W-0h

Table 20-204 RECHARGETRIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	TRIG	R/W	0h	Recharge trigger. 0: No effect. 1: Request VDDR recharge. Request VDDR recharge only when AUX_EVCTL:EVSTAT2.PWR_DWN is 1. Follow this sequence when OPMODEREQ.REQ is LP: - Set TRIG. - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 1. - Clear TRIG. - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 0. Follow this sequence when OPMODEREQ.REQ is PDA or PDLP: - Set TRIG. - Clear TRIG.

20.8.9.30 RECHARGEDET Register (Offset = 78h) [Reset = 00000000h]

RECHARGEDET is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RECHARGEDET_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RECHARGEDET_TABLE.

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VDDR Recharge Detection
Some applications can be sensitive to power noise caused by recharge of VDDR. You can detect if VDDR recharge occurs.

Figure 20-183 RECHARGEDET Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						STAT	EN
R-0h						R-0h	R/W-0h

Table 20-205 RECHARGEDET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	STAT	R	0h	VDDR recharge detector status. 0: No recharge of VDDR has occurred since EN was set. 1: Recharge of VDDR has occurred since EN was set.
0	EN	R/W	0h	VDDR recharge detector enable. 0: Disable recharge detection. STAT becomes zero. 1: Enable recharge detection.

20.8.9.31 RTCSUBSECINC0 Register (Offset = 7Ch) [Reset = 00000000h]

RTCSUBSECINC0 is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSECINC0_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSECINC0_TABLE.

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Real Time Counter Sub Second Increment 0
INC15_0 will replace bits 15:0 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.

Figure 20-184 RTCSUBSECINC0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																INC15_0
R-0h																R/W-0h

Table 20-206 RTCSUBSECINC0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	INC15_0	R/W	0h	New value for bits 15:0 in AON_RTC:SUBSECINC.

20.8.9.32 RTCSUBSECINC1 Register (Offset = 80h) [Reset = 00000000h]

RTCSUBSECINC1 is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSECINC1_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSECINC1_TABLE.

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Real Time Counter Sub Second Increment 1
INC23_16 will replace bits 23:16 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.

Figure 20-185 RTCSUBSECINC1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								INC23_16
R-0h																								R/W-0h

Table 20-207 RTCSUBSECINC1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	INC23_16	R/W	0h	New value for bits 23:16 in AON_RTC:SUBSECINC.

20.8.9.33 RTCSUBSECINCCTL Register (Offset = 84h) [Reset = 00000000h]

RTCSUBSECINCCTL is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSECINCCTL_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSECINCCTL_TABLE.

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Real Time Counter Sub Second Increment Control

Figure 20-186 RTCSUBSECINCCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						UPD_ACK	UPD_REQ
R-0h						R-0h	R/W-0h

Table 20-208 RTCSUBSECINCCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	UPD_ACK	R	0h	Update acknowledgement. 0: AON_RTC has not acknowledged UPD_REQ. 1: AON_RTC has acknowledged UPD_REQ.
0	UPD_REQ	R/W	0h	Request AON_RTC to update AON_RTC:SUBSECINC. 0: Clear request to update. 1: Set request to update. Only change UPD_REQ when it equals UPD_ACK. Clear UPD_REQ after UPD_ACK is 1.

20.8.9.34 RTCSEC Register (Offset = 88h) [Reset = 00000000h]

RTCSEC is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSEC_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSEC_TABLE.

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Real Time Counter Second
System CPU must not access this register. Instead, system CPU must access AON_RTC:SEC.VALUE directly.

Figure 20-187 RTCSEC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																SEC
R-0h																R-0h

Table 20-209 RTCSEC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	SEC	R	0h	Bits 15:0 in AON_RTC:SEC.VALUE. Follow this procedure to get the correct value: - Do two dummy reads of SEC. - Then read SEC until two consecutive reads are equal.

20.8.9.35 RTCSUBSEC Register (Offset = 8Ch) [Reset = 00000000h]

RTCSUBSEC is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSEC_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCSUBSEC_TABLE.

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Real Time Counter Sub-Second
System CPU must not access this register. Instead, system CPU must access AON_RTC:SUBSEC.VALUE directly.

Figure 20-188 RTCSUBSEC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																SUBSEC
R-0h																R-0h

Table 20-210 RTCSUBSEC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	SUBSEC	R	0h	Bits 31:16 in AON_RTC:SUBSEC.VALUE. Follow this procedure to get the correct value: - Do two dummy reads SUBSEC. - Then read SUBSEC until two consecutive reads are equal.

20.8.9.36 RTCEVCLR Register (Offset = 90h) [Reset = 00000000h]

RTCEVCLR is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCEVCLR_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_RTCEVCLR_TABLE.

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AON_RTC Event Clear
Request to clear events:
- AON_RTC:EVFLAGS.CH2.
- AON_RTC:EVFLAGS.CH2 delayed version.
- AUX_EVCTL:EVSTAT2.AON_RTC_CH2.
- AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY.

Figure 20-189 RTCEVCLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							RTC_CH2_EV_CLR
R-0h							R/W-0h

Table 20-211 RTCEVCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	RTC_CH2_EV_CLR	R/W	0h	Clear events from AON_RTC channel 2. 0: No effect. 1: Clear events from AON_RTC channel 2. Keep RTC_CH2_EV_CLR high until AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY are 0.

20.8.9.37 BATMONBAT Register (Offset = 94h) [Reset = 00000000h]

BATMONBAT is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_BATMONBAT_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_BATMONBAT_TABLE.

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AON_BATMON Battery Voltage Value
Read access to AON_BATMON:BAT. System CPU must not access this register. Instead, system CPU must access AON_BATMON:BAT directly. AON_BATMON:BAT updates during VDDR recharge or active operational mode.

Figure 20-190 BATMONBAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																					INT			FRAC
R-0h																					RH-0h			R-0h

Table 20-212 BATMONBAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R	0h	Reserved
10-8	INT	RH	0h	See AON_BATMON:BAT.INT. Follow this procedure to get the correct value: - Do two dummy reads of INT. - Then read INT until two consecutive reads are equal.
7-0	FRAC	R	0h	See AON_BATMON:BAT.FRAC. Follow this procedure to get the correct value: - Do two dummy reads of FRAC. - Then read FRAC until two consecutive reads are equal.

20.8.9.38 BATMONTEMP Register (Offset = 9Ch) [Reset = 00000000h]

BATMONTEMP is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_BATMONTEMP_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_BATMONTEMP_TABLE.

Return to the Summary Table.

AON_BATMON Temperature Value
Read access to AON_BATMON:TEMP. System CPU must not access this register. Instead, system CPU must access AON_BATMON:TEMP directly. AON_BATMON:TEMP updates during VDDR recharge or active operational mode.

Figure 20-191 BATMONTEMP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN					INT									FRAC
R-0h					RH-0h									R-0h

Table 20-213 BATMONTEMP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-11	SIGN	R	0h	Sign extension of INT. Follow this procedure to get the correct value: - Do two dummy reads of SIGN. - Then read SIGN until two consecutive reads are equal.
10-2	INT	RH	0h	See AON_BATMON:TEMP.INT. Follow this procedure to get the correct value: - Do two dummy reads of INT. - Then read INT until two consecutive reads are equal.
1-0	FRAC	R	0h	See AON_BATMON:TEMP.FRAC. Follow this procedure to get the correct value: - Do two dummy reads of FRAC. - Then read FRAC until two consecutive reads are equal.

20.8.9.39 TIMERHALT Register (Offset = A0h) [Reset = 00000000h]

TIMERHALT is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMERHALT_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMERHALT_TABLE.

Return to the Summary Table.

Timer Halt
Debug register

Figure 20-192 TIMERHALT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				PROGDLY	AUX_TIMER2	AUX_TIMER1	AUX_TIMER0
R-0h				RH/W-0h	RH/W-0h	RH/W-0h	RH/W-0h

Table 20-214 TIMERHALT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	PROGDLY	RH/W	0h	Halt programmable delay. 0: AUX_EVCTL:PROGDLY.VALUE decrements as normal. 1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation.
2	AUX_TIMER2	RH/W	0h	Halt AUX_TIMER2. 0: AUX_TIMER2 operates as normal. 1: Halt AUX_TIMER2 operation.
1	AUX_TIMER1	RH/W	0h	Halt AUX_TIMER01 Timer 1. 0: AUX_TIMER01 Timer 1 operates as normal. 1: Halt AUX_TIMER01 Timer 1 operation.
0	AUX_TIMER0	RH/W	0h	Halt AUX_TIMER01 Timer 0. 0: AUX_TIMER01 Timer 0 operates as normal. 1: Halt AUX_TIMER01 Timer 0 operation.

20.8.9.40 TIMER2BRIDGE Register (Offset = B0h) [Reset = 00000000h]

TIMER2BRIDGE is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2BRIDGE_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_TIMER2BRIDGE_TABLE.

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AUX_TIMER2 Bridge

Figure 20-193 TIMER2BRIDGE Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							BUSY
R-0h							R-0h

Table 20-215 TIMER2BRIDGE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	BUSY	R	0h	Status of bus transactions to AUX_TIMER2. 0: No unfinished bus transactions. 1: A bus transaction is ongoing.

20.8.9.41 SWPWRPROF Register (Offset = B4h) [Reset = 00000000h]

SWPWRPROF is shown in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_SWPWRPROF_FIGURE and described in #AUX_SYSIF_AUX_SYSIF_MMAP_AUX_SYSIF_AUX_SYSIF_ALL_SWPWRPROF_TABLE.

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Software Power Profiler

Figure 20-194 SWPWRPROF Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													STAT
R-0h													R/W-0h

Table 20-216 SWPWRPROF Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	STAT	R/W	0h	Software status bits that can be read by the power profiler.