SWCU192 User guide

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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265
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275
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        382
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                384
        
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                578
        
                579
      5. 580
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    3. 582
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                589
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                602
        
                 603
        
                604
        
                 605
        
                606
        
                 607
      6. 608
5. 609
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                637
        
                638
  5. 639
    1. 640
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                645
        
                646
        
                647
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                649
        
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                651
        
                652
      5. 653
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                668
        
                669
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  7. 675
7. 676
8. 677
  1. 678
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  3. 680
  4. 681
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  10. 687
  11. 688
  12. 689
690
1. 691
2. 692
3. 693
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695
1. 696
2. 697
3. 698
4. 699
  1. 700
  2. 701
  3. 702
  4. 703
    1. 704
    2. 705
      1. 706
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  5. 708
  6. 709
  7. 710
5. 711
6. 712
7. 713
  1. 714
715
1. 716
2. 717
3. 718
4. 719
  1. 720
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  3. 724
  4. 725
    1. 726
    2. 727
      1. 728
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    3. 730
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    6. 733
    7. 734
5. 735
6. 736
7. 737
  1. 738
739
1. 740
2. 741
3. 742
  1. 743
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    5. 748
  2. 749
    1. 750
  3. 751
    1. 752
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  5. 755
    1. 756
    2. 757
4. 758
5. 759
  1. 760
761
1. 762
2. 763
3. 764
4. 765
  1. 766
    1. 767
  2. 768
  3. 769
  4. 770
    1. 771
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    1. 773
  6. 774
    1. 775
  7. 776
    1. 777
  8. 778
    1. 779
    2. 780
5. 781
  1. 782
  2. 783
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  4. 785
    1. 786
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    3. 788
6. 789
  1. 790
  2. 791
  3. 792
  4. 793
7. 794
8. 795
  1. 796
  2. 797
9. 798
  1. 799
800
1. 801
  1. 802
2. 803
  1. 804
  2. 805
  3. 806
    1. 807
    2. 808
    3. 809
  4. 810
    1. 811
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    3. 813
3. 814
  1. 815
  2. 816
    1. 817
    2. 818
    3. 819
    4. 820
    5. 821
      1. 822
      2. 823
      3. 824
    6. 825
      1. 826
    7. 827
      1. 828
      2. 829
      3. 830
      4. 831
    8. 832
  3. 833
    1. 834
      1. 835
      2. 836
      3. 837
      4. 838
      5. 839
      6. 840
      7. 841
      8. 842
      9. 843
      10. 844
      11. 845
      12. 846
      13. 847
      14. 848
    2. 849
      1. 850
      2. 851
      3. 852
      4. 853
      5. 854
      6. 855
      7. 856
      8. 857
      9. 858
      10. 859
      11. 860
      12. 861
      13. 862
      14. 863
      15. 864
      16. 865
      17. 866
      18. 867
      19. 868
      20. 869
  4. 870
    1. 871
    2. 872
    3. 873
    4. 874
    5. 875
4. 876
  1. 877
    1. 878
    2. 879
    3. 880
    4. 881
    5. 882
  2. 883
    1. 884
    2. 885
5. 886
  1. 887
    1. 888
    2. 889
    3. 890
    4. 891
  2. 892
  3. 893
    1. 894
    2. 895
  4. 896
    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
      4. 903
      5. 904
    2. 905
    3. 906
    4. 907
    5. 908
    6. 909
  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
    5. 915
    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
  2. 927
8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
    3. 939
    4. 940
  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
    2. 947
    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

20.8.5 AUX_TDC Registers

#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_TABLE_1 lists the memory-mapped registers for the AUX_TDC registers. All register offset addresses not listed in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 20-113 AUX_TDC Registers

Offset	Acronym	Register Name	Section
0h	CTL	Control	#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_CTL
4h	STAT	Status	#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_STAT
8h	RESULT	Result	#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_RESULT
Ch	SATCFG	Saturation Configuration	#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_SATCFG
10h	TRIGSRC	Trigger Source	#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGSRC
14h	TRIGCNT	Trigger Counter	#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGCNT
18h	TRIGCNTLOAD	Trigger Counter Load	#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGCNTLOAD
1Ch	TRIGCNTCFG	Trigger Counter Configuration	#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGCNTCFG
20h	PRECTL	Prescaler Control	#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_PRECTL
24h	PRECNTR	Prescaler Counter	#AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_PRECNTR

Complex bit access types are encoded to fit into small table cells. #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_LEGEND shows the codes that are used for access types in this section.

Table 20-114 AUX_TDC Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

20.8.5.1 CTL Register (Offset = 0h) [Reset = 00000000h]

CTL is shown in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_CTL_FIGURE and described in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_CTL_TABLE.

Return to the Summary Table.

Control

Figure 20-101 CTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														CMD
R-0h														W-0h

Table 20-115 CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	CMD	W	0h	TDC commands. 0h = Clear STAT.SAT, STAT.DONE, and RESULT.VALUE. This is not needed as prerequisite for a measurement. Reliable clear is only guaranteed from IDLE state. 1h = Synchronous counter start. The counter looks for the opposite edge of the selected start event before it starts to count when the selected edge occurs. This guarantees an edge-triggered start and is recommended for frequency measurements. 2h = Asynchronous counter start. The counter starts to count when the start event is high. To achieve precise edge-to-edge measurements you must ensure that the start event is low for at least 420 ns after you write this command. 3h = Force TDC state machine back to IDLE state. Never write this command while AUX_TDC:STAT.STATE equals CLR_CNT or WAIT_CLR_CNT_DONE.

Bit

Field

Type

Reset

Description

31-2

RESERVED

Reserved

1-0

CMD

TDC commands.

0h = Clear STAT.SAT, STAT.DONE, and RESULT.VALUE.
This is not needed as prerequisite for a measurement. Reliable clear is only guaranteed from IDLE state.

1h = Synchronous counter start.
The counter looks for the opposite edge of the selected start event before it starts to count when the selected edge occurs. This guarantees an edge-triggered start and is recommended for frequency measurements.

2h = Asynchronous counter start.
The counter starts to count when the start event is high. To achieve precise edge-to-edge measurements you must ensure that the start event is low for at least 420 ns after you write this command.

3h = Force TDC state machine back to IDLE state.
Never write this command while AUX_TDC:STAT.STATE equals CLR_CNT or WAIT_CLR_CNT_DONE.

20.8.5.2 STAT Register (Offset = 4h) [Reset = 00000006h]

STAT is shown in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_STAT_FIGURE and described in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_STAT_TABLE.

Return to the Summary Table.

Status

Figure 20-102 STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
SAT	DONE	STATE
R-0h	R-0h	R-6h

Table 20-116 STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	SAT	R	0h	TDC measurement saturation flag. 0: Conversion has not saturated. 1: Conversion stopped due to saturation. This field is cleared when a new measurement is started or when CLR_RESULT is written to CTL.CMD.
6	DONE	R	0h	TDC measurement complete flag. 0: TDC measurement has not yet completed. 1: TDC measurement has completed. This field clears when a new TDC measurement starts or when you write CLR_RESULT to CTL.CMD.
5-0	STATE	R	6h	TDC state machine status. 0h = Current state is TDC_STATE_WAIT_START. The fast-counter circuit looks for the start condition. The state machine waits for the fast-counter to increment. 4h = Current state is TDC_STATE_WAIT_STARTSTOPCNTEN. The fast-counter circuit looks for the start condition. The state machine waits for the fast-counter to increment. 6h = Current state is TDC_STATE_IDLE. This is the default state after reset and abortion. State will change when you write CTL.CMD to either RUN_SYNC_START or RUN. 7h = Current state is TDC_STATE_CLRCNT. The fast-counter circuit is reset. 8h = Current state is TDC_STATE_WAIT_STOP. The state machine waits for the fast-counter circuit to stop. Ch = Current state is TDC_STATE_WAIT_STOPCNTDOWN. The fast-counter circuit looks for the stop condition. It will ignore a number of stop events configured in TRIGCNTLOAD.CNT. Eh = Current state is TDC_STATE_GETRESULTS. The state machine copies the counter value from the fast-counter circuit. Fh = Current state is TDC_STATE_POR. This is the reset state. 16h = Current state is TDC_STATE_WAIT_CLRCNT_DONE. The state machine waits for fast-counter circuit to finish reset. 1Eh = Current state is TDC_WAIT_STARTFALL. The fast-counter circuit waits for a falling edge on the start event. 2Eh = Current state is TDC_FORCESTOP. You wrote ABORT to CTL.CMD to abort the TDC measurement.

20.8.5.3 RESULT Register (Offset = 8h) [Reset = 00000002h]

RESULT is shown in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_RESULT_FIGURE and described in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_RESULT_TABLE.

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Result
Result of last TDC conversion.

Figure 20-103 RESULT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED							VALUE
R-0h							R-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VALUE
R-2h

Table 20-117 RESULT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24-0	VALUE	R	2h	TDC conversion result. The result of the TDC conversion is given in number of clock edges of the clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and falling edges are counted. If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it takes a non-zero time to stop the measurement. Hence, the maximum value of this field becomes slightly higher than 2²⁴ if you configure SATCFG.LIMIT to R24.

20.8.5.4 SATCFG Register (Offset = Ch) [Reset = 0000000Fh]

SATCFG is shown in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_SATCFG_FIGURE and described in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_SATCFG_TABLE.

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Saturation Configuration

Figure 20-104 SATCFG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												LIMIT
R-0h												R/W-Fh

Table 20-118 SATCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	LIMIT	R/W	Fh	Saturation limit. The flag STAT.SAT is set when the TDC counter saturates. Values not enumerated are not supported 3h = Result bit 12: TDC conversion saturates and stops when RESULT.VALUE[12] is set. 4h = Result bit 13: TDC conversion saturates and stops when RESULT.VALUE[13] is set. 5h = Result bit 14: TDC conversion saturates and stops when RESULT.VALUE[14] is set. 6h = Result bit 15: TDC conversion saturates and stops when RESULT.VALUE[15] is set. 7h = Result bit 16: TDC conversion saturates and stops when RESULT.VALUE[16] is set. 8h = Result bit 17: TDC conversion saturates and stops when RESULT.VALUE[17] is set. 9h = Result bit 18: TDC conversion saturates and stops when RESULT.VALUE[18] is set. Ah = Result bit 19: TDC conversion saturates and stops when RESULT.VALUE[19] is set. Bh = Result bit 20: TDC conversion saturates and stops when RESULT.VALUE[20] is set. Ch = Result bit 21: TDC conversion saturates and stops when RESULT.VALUE[21] is set. Dh = Result bit 22: TDC conversion saturates and stops when RESULT.VALUE[22] is set. Eh = Result bit 23: TDC conversion saturates and stops when RESULT.VALUE[23] is set. Fh = Result bit 24: TDC conversion saturates and stops when RESULT.VALUE[24] is set.

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

LIMIT

R/W

Saturation limit.
The flag STAT.SAT is set when the TDC counter saturates.
Values not enumerated are not supported

3h = Result bit 12: TDC conversion saturates and stops when RESULT.VALUE[12] is set.

4h = Result bit 13: TDC conversion saturates and stops when RESULT.VALUE[13] is set.

5h = Result bit 14: TDC conversion saturates and stops when RESULT.VALUE[14] is set.

6h = Result bit 15: TDC conversion saturates and stops when RESULT.VALUE[15] is set.

7h = Result bit 16: TDC conversion saturates and stops when RESULT.VALUE[16] is set.

8h = Result bit 17: TDC conversion saturates and stops when RESULT.VALUE[17] is set.

9h = Result bit 18: TDC conversion saturates and stops when RESULT.VALUE[18] is set.

Ah = Result bit 19: TDC conversion saturates and stops when RESULT.VALUE[19] is set.

Bh = Result bit 20: TDC conversion saturates and stops when RESULT.VALUE[20] is set.

Ch = Result bit 21: TDC conversion saturates and stops when RESULT.VALUE[21] is set.

Dh = Result bit 22: TDC conversion saturates and stops when RESULT.VALUE[22] is set.

Eh = Result bit 23: TDC conversion saturates and stops when RESULT.VALUE[23] is set.

Fh = Result bit 24: TDC conversion saturates and stops when RESULT.VALUE[24] is set.

20.8.5.5 TRIGSRC Register (Offset = 10h) [Reset = 00000000h]

TRIGSRC is shown in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGSRC_FIGURE and described in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGSRC_TABLE.

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Trigger Source
Select source and polarity for TDC start and stop events. See the Technical Reference Manual for event timing requirements.

Figure 20-105 TRIGSRC Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED	STOP_POL	STOP_SRC
R-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	START_POL	START_SRC
R-0h	R/W-0h	R/W-0h

Table 20-119 TRIGSRC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-15	RESERVED	R	0h	Reserved
14	STOP_POL	R/W	0h	Polarity of stop source. Change only while STAT.STATE is IDLE. 0h = TDC conversion stops when high level is detected. 1h = TDC conversion stops when low level is detected.
13-8	STOP_SRC	R/W	0h	Select stop source from the asynchronous AUX event bus. Change only while STAT.STATE is IDLE. 0h = AUX_EVCTL:EVSTAT0.AUXIO0 1h = AUX_EVCTL:EVSTAT0.AUXIO1 2h = AUX_EVCTL:EVSTAT0.AUXIO2 3h = AUX_EVCTL:EVSTAT0.AUXIO3 4h = AUX_EVCTL:EVSTAT0.AUXIO4 5h = AUX_EVCTL:EVSTAT0.AUXIO5 6h = AUX_EVCTL:EVSTAT0.AUXIO6 7h = AUX_EVCTL:EVSTAT0.AUXIO7 8h = AUX_EVCTL:EVSTAT0.AUXIO8 9h = AUX_EVCTL:EVSTAT0.AUXIO9 Ah = AUX_EVCTL:EVSTAT0.AUXIO10 Bh = AUX_EVCTL:EVSTAT0.AUXIO11 Ch = AUX_EVCTL:EVSTAT0.AUXIO12 Dh = AUX_EVCTL:EVSTAT0.AUXIO13 Eh = AUX_EVCTL:EVSTAT0.AUXIO14 Fh = AUX_EVCTL:EVSTAT0.AUXIO15 10h = AUX_EVCTL:EVSTAT1.AUXIO16 11h = AUX_EVCTL:EVSTAT1.AUXIO17 12h = AUX_EVCTL:EVSTAT1.AUXIO18 13h = AUX_EVCTL:EVSTAT1.AUXIO19 14h = AUX_EVCTL:EVSTAT1.AUXIO20 15h = AUX_EVCTL:EVSTAT1.AUXIO21 16h = AUX_EVCTL:EVSTAT1.AUXIO22 17h = AUX_EVCTL:EVSTAT1.AUXIO23 18h = AUX_EVCTL:EVSTAT1.AUXIO24 19h = AUX_EVCTL:EVSTAT1.AUXIO25 1Ah = AUX_EVCTL:EVSTAT1.AUXIO26 1Bh = AUX_EVCTL:EVSTAT1.AUXIO27 1Ch = AUX_EVCTL:EVSTAT1.AUXIO28 1Dh = AUX_EVCTL:EVSTAT1.AUXIO29 1Eh = AUX_EVCTL:EVSTAT1.AUXIO30 1Fh = AUX_EVCTL:EVSTAT1.AUXIO31 20h = AUX_EVCTL:EVSTAT2.MANUAL_EV 21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2 22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 26h = AUX_EVCTL:EVSTAT2.SCLK_LF 27h = AUX_EVCTL:EVSTAT2.PWR_DWN 28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE 29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF 2Bh = AUX_EVCTL:EVSTAT2.MCU_EV 2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA 2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB 30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Eh = Select TDC Prescaler event which is generated by configuration of PRECTL. 3Fh = No event.
7	RESERVED	R	0h	Reserved
6	START_POL	R/W	0h	Polarity of start source. Change only while STAT.STATE is IDLE. 0h = TDC conversion starts when high level is detected. 1h = TDC conversion starts when low level is detected.
5-0	START_SRC	R/W	0h	Select start source from the asynchronous AUX event bus. Change only while STAT.STATE is IDLE. 0h = AUX_EVCTL:EVSTAT0.AUXIO0 1h = AUX_EVCTL:EVSTAT0.AUXIO1 2h = AUX_EVCTL:EVSTAT0.AUXIO2 3h = AUX_EVCTL:EVSTAT0.AUXIO3 4h = AUX_EVCTL:EVSTAT0.AUXIO4 5h = AUX_EVCTL:EVSTAT0.AUXIO5 6h = AUX_EVCTL:EVSTAT0.AUXIO6 7h = AUX_EVCTL:EVSTAT0.AUXIO7 8h = AUX_EVCTL:EVSTAT0.AUXIO8 9h = AUX_EVCTL:EVSTAT0.AUXIO9 Ah = AUX_EVCTL:EVSTAT0.AUXIO10 Bh = AUX_EVCTL:EVSTAT0.AUXIO11 Ch = AUX_EVCTL:EVSTAT0.AUXIO12 Dh = AUX_EVCTL:EVSTAT0.AUXIO13 Eh = AUX_EVCTL:EVSTAT0.AUXIO14 Fh = AUX_EVCTL:EVSTAT0.AUXIO15 10h = AUX_EVCTL:EVSTAT1.AUXIO16 11h = AUX_EVCTL:EVSTAT1.AUXIO17 12h = AUX_EVCTL:EVSTAT1.AUXIO18 13h = AUX_EVCTL:EVSTAT1.AUXIO19 14h = AUX_EVCTL:EVSTAT1.AUXIO20 15h = AUX_EVCTL:EVSTAT1.AUXIO21 16h = AUX_EVCTL:EVSTAT1.AUXIO22 17h = AUX_EVCTL:EVSTAT1.AUXIO23 18h = AUX_EVCTL:EVSTAT1.AUXIO24 19h = AUX_EVCTL:EVSTAT1.AUXIO25 1Ah = AUX_EVCTL:EVSTAT1.AUXIO26 1Bh = AUX_EVCTL:EVSTAT1.AUXIO27 1Ch = AUX_EVCTL:EVSTAT1.AUXIO28 1Dh = AUX_EVCTL:EVSTAT1.AUXIO29 1Eh = AUX_EVCTL:EVSTAT1.AUXIO30 1Fh = AUX_EVCTL:EVSTAT1.AUXIO31 20h = AUX_EVCTL:EVSTAT2.MANUAL_EV 21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2 22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 26h = AUX_EVCTL:EVSTAT2.SCLK_LF 27h = AUX_EVCTL:EVSTAT2.PWR_DWN 28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE 29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF 2Bh = AUX_EVCTL:EVSTAT2.MCU_EV 2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA 2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB 30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Eh = Select TDC Prescaler event which is generated by configuration of PRECTL. 3Fh = No event.

20.8.5.6 TRIGCNT Register (Offset = 14h) [Reset = 00000000h]

TRIGCNT is shown in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGCNT_FIGURE and described in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGCNT_TABLE.

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Trigger Counter
Stop-counter control and status.

Figure 20-106 TRIGCNT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																CNT
R-0h																R/W-0h

Table 20-120 TRIGCNT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	CNT	R/W	0h	Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. Read CNT to get the remaining number of stop events to ignore during a TDC measurement. Write CNT to update the remaining number of stop events to ignore during a TDC measurement. The TDC measurement ignores updates of CNT if there are no more stop events left to ignore. When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the start of the measurement.

20.8.5.7 TRIGCNTLOAD Register (Offset = 18h) [Reset = 00000000h]

TRIGCNTLOAD is shown in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGCNTLOAD_FIGURE and described in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGCNTLOAD_TABLE.

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Trigger Counter Load
Stop-counter load.

Figure 20-107 TRIGCNTLOAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																CNT
R-0h																R/W-0h

Table 20-121 TRIGCNTLOAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	CNT	R/W	0h	Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. To measure frequency of an event source: - Set start event equal to stop event. - Set CNT to number of periods to measure. Both 0 and 1 values measures a single event source period. To measure pulse width of an event source: - Set start event source equal to stop event source. - Select different polarity for start and stop event. - Set CNT to 0. To measure time from the start event to the Nth stop event when N > 1: - Select different start and stop event source. - Set CNT to (N-1). See the Technical Reference Manual for event timing requirements. When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start of the measurement.

20.8.5.8 TRIGCNTCFG Register (Offset = 1Ch) [Reset = 00000000h]

TRIGCNTCFG is shown in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGCNTCFG_FIGURE and described in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_TRIGCNTCFG_TABLE.

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Trigger Counter Configuration
Stop-counter configuration.

Figure 20-108 TRIGCNTCFG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															EN
R-0h															R/W-0h

Table 20-122 TRIGCNTCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EN	R/W	0h	Enable stop-counter. 0: Disable stop-counter. 1: Enable stop-counter. Change only while STAT.STATE is IDLE.

20.8.5.9 PRECTL Register (Offset = 20h) [Reset = 0000003Fh]

PRECTL is shown in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_PRECTL_FIGURE and described in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_PRECTL_TABLE.

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Prescaler Control
The prescaler can be used to count events that are faster than the AUX bus rate.
It can be used to:
- count pulses on a specified event from the asynchronous event bus.
- prescale a specified event from the asynchronous event bus.
To use the prescaler output as an event source in TDC measurements you must set both TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to AUX_TDC_PRE.
It is recommended to use the prescaler when the signal frequency to measure exceeds 1/10th of the AUX bus rate.

Figure 20-109 PRECTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESET_N	RATIO	SRC
R/W-0h	R/W-0h	R/W-3Fh

Table 20-123 PRECTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	RESET_N	R/W	0h	Prescaler reset. 0: Reset prescaler. 1: Release reset of prescaler. AUX_TDC_PRE event becomes 0 when you reset the prescaler.
6	RATIO	R/W	0h	Prescaler ratio. This controls how often the AUX_TDC_PRE event is generated by the prescaler. 0h = Prescaler divides input by 16. AUX_TDC_PRE event has a rising edge for every 16 rising edges of the input. AUX_TDC_PRE event toggles on every 8th rising edge of the input. 1h = Prescaler divides input by 64. AUX_TDC_PRE event has a rising edge for every 64 rising edges of the input. AUX_TDC_PRE event toggles on every 32nd rising edge of the input.
5-0	SRC	R/W	3Fh	Prescaler event source. Select an event from the asynchronous AUX event bus to connect to the prescaler input. Configure only while RESET_N is 0. 0h = AUX_EVCTL:EVSTAT0.AUXIO0 1h = AUX_EVCTL:EVSTAT0.AUXIO1 2h = AUX_EVCTL:EVSTAT0.AUXIO2 3h = AUX_EVCTL:EVSTAT0.AUXIO3 4h = AUX_EVCTL:EVSTAT0.AUXIO4 5h = AUX_EVCTL:EVSTAT0.AUXIO5 6h = AUX_EVCTL:EVSTAT0.AUXIO6 7h = AUX_EVCTL:EVSTAT0.AUXIO7 8h = AUX_EVCTL:EVSTAT0.AUXIO8 9h = AUX_EVCTL:EVSTAT0.AUXIO9 Ah = AUX_EVCTL:EVSTAT0.AUXIO10 Bh = AUX_EVCTL:EVSTAT0.AUXIO11 Ch = AUX_EVCTL:EVSTAT0.AUXIO12 Dh = AUX_EVCTL:EVSTAT0.AUXIO13 Eh = AUX_EVCTL:EVSTAT0.AUXIO14 Fh = AUX_EVCTL:EVSTAT0.AUXIO15 10h = AUX_EVCTL:EVSTAT1.AUXIO16 11h = AUX_EVCTL:EVSTAT1.AUXIO17 12h = AUX_EVCTL:EVSTAT1.AUXIO18 13h = AUX_EVCTL:EVSTAT1.AUXIO19 14h = AUX_EVCTL:EVSTAT1.AUXIO20 15h = AUX_EVCTL:EVSTAT1.AUXIO21 16h = AUX_EVCTL:EVSTAT1.AUXIO22 17h = AUX_EVCTL:EVSTAT1.AUXIO23 18h = AUX_EVCTL:EVSTAT1.AUXIO24 19h = AUX_EVCTL:EVSTAT1.AUXIO25 1Ah = AUX_EVCTL:EVSTAT1.AUXIO26 1Bh = AUX_EVCTL:EVSTAT1.AUXIO27 1Ch = AUX_EVCTL:EVSTAT1.AUXIO28 1Dh = AUX_EVCTL:EVSTAT1.AUXIO29 1Eh = AUX_EVCTL:EVSTAT1.AUXIO30 1Fh = AUX_EVCTL:EVSTAT1.AUXIO31 20h = AUX_EVCTL:EVSTAT2.MANUAL_EV 21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2 22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 26h = AUX_EVCTL:EVSTAT2.SCLK_LF 27h = AUX_EVCTL:EVSTAT2.PWR_DWN 28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE 29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF 2Bh = AUX_EVCTL:EVSTAT2.MCU_EV 2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA 2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB 30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Fh = No event.

20.8.5.10 PRECNTR Register (Offset = 24h) [Reset = 00000000h]

PRECNTR is shown in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_PRECNTR_FIGURE and described in #AUX_TDC_AUX_TDC_MMAP_AUX_TDC_AUX_TDC_ALL_PRECNTR_TABLE.

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Prescaler Counter

Figure 20-110 PRECNTR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																CNT
R-0h																R/W-0h

Table 20-124 PRECNTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	CNT	R/W	0h	Prescaler counter value. Write a value to CNT to capture the value of the 16-bit prescaler counter into CNT. Read CNT to get the captured value. The read value gets 1 LSB uncertainty if the event source level rises when you release the reset. The read value gets 1 LSB uncertainty if the event source level rises when you capture the prescaler counter. Please note the following: - The prescaler counter is reset to 2 by PRECTL.RESET_N. - The captured value is 2 when the number of rising edges on prescaler input is less than 3. Otherwise, captured value equals number of event pulses - 1.