SWCU192 User guide

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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        382
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                602
        
                 603
        
                604
        
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                637
        
                638
  5. 639
    1. 640
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                645
        
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                647
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                649
        
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                652
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                668
        
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7. 676
8. 677
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690
1. 691
2. 692
3. 693
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695
1. 696
2. 697
3. 698
4. 699
  1. 700
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  4. 703
    1. 704
    2. 705
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  6. 709
  7. 710
5. 711
6. 712
7. 713
  1. 714
715
1. 716
2. 717
3. 718
4. 719
  1. 720
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    1. 726
    2. 727
      1. 728
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5. 735
6. 736
7. 737
  1. 738
739
1. 740
2. 741
3. 742
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  2. 749
    1. 750
  3. 751
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    1. 756
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4. 758
5. 759
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761
1. 762
2. 763
3. 764
4. 765
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  2. 768
  3. 769
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    1. 777
  8. 778
    1. 779
    2. 780
5. 781
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6. 789
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7. 794
8. 795
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9. 798
  1. 799
800
1. 801
  1. 802
2. 803
  1. 804
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  3. 806
    1. 807
    2. 808
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  4. 810
    1. 811
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    3. 813
3. 814
  1. 815
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    3. 819
    4. 820
    5. 821
      1. 822
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    6. 825
      1. 826
    7. 827
      1. 828
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    8. 832
  3. 833
    1. 834
      1. 835
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      6. 840
      7. 841
      8. 842
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      10. 844
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      12. 846
      13. 847
      14. 848
    2. 849
      1. 850
      2. 851
      3. 852
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      7. 856
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      12. 861
      13. 862
      14. 863
      15. 864
      16. 865
      17. 866
      18. 867
      19. 868
      20. 869
  4. 870
    1. 871
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4. 876
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  2. 883
    1. 884
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5. 886
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    1. 888
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    1. 894
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    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
      4. 903
      5. 904
    2. 905
    3. 906
    4. 907
    5. 908
    6. 909
  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
    5. 915
    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
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8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
    3. 939
    4. 940
  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
    2. 947
    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

3.9.2 CPU_FPB Registers

#CPU_FPB_CPU_FPB_MAP1_TABLE_1 lists the memory-mapped registers for the CPU_FPB registers. All register offset addresses not listed in #CPU_FPB_CPU_FPB_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 3-55 CPU_FPB Registers

Offset	Acronym	Register Name	Section
0h	CTRL	Control	#CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_CTRL
4h	REMAP	Remap	#CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_REMAP
8h	COMP0	Comparator 0	#CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP0
Ch	COMP1	Comparator 1	#CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP1
10h	COMP2	Comparator 2	#CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP2
14h	COMP3	Comparator 3	#CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP3
18h	COMP4	Comparator 4	#CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP4
1Ch	COMP5	Comparator 5	#CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP5
20h	COMP6	Comparator 6	#CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP6
24h	COMP7	Comparator 7	#CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP7

Complex bit access types are encoded to fit into small table cells. #CPU_FPB_CPU_FPB_MAP1_LEGEND shows the codes that are used for access types in this section.

Table 3-56 CPU_FPB Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

3.9.2.1 CTRL Register (Offset = 0h) [Reset = 00000260h]

CTRL is shown in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_CTRL_FIGURE and described in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_CTRL_TABLE.

Return to the Summary Table.

Control
This register is used to enable the flash patch block.

Figure 3-25 CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED		NUM_CODE2		NUM_LIT
R-0h		R-0h		R-2h

7	6	5	4	3	2	1	0
NUM_CODE1				RESERVED		KEY	ENABLE
R-6h				R-0h		W-0h	R/W-0h

Table 3-57 CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-14	RESERVED	R	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
13-12	NUM_CODE2	R	0h	Number of full banks of code comparators, sixteen comparators per bank. Where less than sixteen code comparators are provided, the bank count is zero, and the number present indicated by NUM_CODE1. This read only field contains 3'b000 to indicate 0 banks for Cortex-M processor.
11-8	NUM_LIT	R	2h	Number of literal slots field. 0x0: No literal slots 0x2: Two literal slots
7-4	NUM_CODE1	R	6h	Number of code slots field. 0x0: No code slots 0x2: Two code slots 0x6: Six code slots
3-2	RESERVED	R	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1	KEY	W	0h	Key field. In order to write to this register, this bit-field must be written to '1'. This bit always reads 0.
0	ENABLE	R/W	0h	Flash patch unit enable bit 0x0: Flash patch unit disabled 0x1: Flash patch unit enabled

3.9.2.2 REMAP Register (Offset = 4h) [Reset = X]

REMAP is shown in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_REMAP_FIGURE and described in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_REMAP_TABLE.

Return to the Summary Table.

Remap
This register provides the remap base address location where a matched addresses are remapped. The three most significant bits and the five least significant bits of the remap base address are hard-coded to 3'b001 and 5'b00000 respectively. The remap base address must be in system space and is it required to be 8-word aligned, with one word allocated to each of the eight FPB comparators.

Figure 3-26 REMAP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			REMAP
R-1h			R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REMAP											RESERVED
R/W-X											R-0h

Table 3-58 REMAP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R	1h	This field always reads 3'b001. Writing to this field is ignored.
28-5	REMAP	R/W	X	Remap base address field.
4-0	RESERVED	R	0h	This field always reads 0. Writing to this field is ignored.

3.9.2.3 COMP0 Register (Offset = 8h) [Reset = 00000000h]

COMP0 is shown in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP0_FIGURE and described in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP0_TABLE.

Return to the Summary Table.

Comparator 0

Figure 3-27 COMP0 Register

31	30	29	28	27	26	25	24
REPLACE		RESERVED	COMP
R/W-0h		R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
COMP
R/W-0h

15	14	13	12	11	10	9	8
COMP
R/W-0h

7	6	5	4	3	2	1	0
COMP						RESERVED	ENABLE
R/W-0h						R/W-0h	R/W-0h

Table 3-59 COMP0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	REPLACE	R/W	0h	This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords.
29	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28-2	COMP	R/W	0h	Comparison address.
1	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0	ENABLE	R/W	0h	Compare and remap enable comparator 0. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 0 disabled 0x1: Compare and remap for comparator 0 enabled

3.9.2.4 COMP1 Register (Offset = Ch) [Reset = 00000000h]

COMP1 is shown in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP1_FIGURE and described in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP1_TABLE.

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Comparator 1

Figure 3-28 COMP1 Register

31	30	29	28	27	26	25	24
REPLACE		RESERVED	COMP
R/W-0h		R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
COMP
R/W-0h

15	14	13	12	11	10	9	8
COMP
R/W-0h

7	6	5	4	3	2	1	0
COMP						RESERVED	ENABLE
R/W-0h						R/W-0h	R/W-0h

Table 3-60 COMP1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	REPLACE	R/W	0h	This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords.
29	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28-2	COMP	R/W	0h	Comparison address.
1	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0	ENABLE	R/W	0h	Compare and remap enable comparator 1. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 1 disabled 0x1: Compare and remap for comparator 1 enabled

3.9.2.5 COMP2 Register (Offset = 10h) [Reset = 00000000h]

COMP2 is shown in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP2_FIGURE and described in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP2_TABLE.

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Comparator 2

Figure 3-29 COMP2 Register

31	30	29	28	27	26	25	24
REPLACE		RESERVED	COMP
R/W-0h		R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
COMP
R/W-0h

15	14	13	12	11	10	9	8
COMP
R/W-0h

7	6	5	4	3	2	1	0
COMP						RESERVED	ENABLE
R/W-0h						R/W-0h	R/W-0h

Table 3-61 COMP2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	REPLACE	R/W	0h	This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords.
29	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28-2	COMP	R/W	0h	Comparison address.
1	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0	ENABLE	R/W	0h	Compare and remap enable comparator 2. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 2 disabled 0x1: Compare and remap for comparator 2 enabled

3.9.2.6 COMP3 Register (Offset = 14h) [Reset = 00000000h]

COMP3 is shown in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP3_FIGURE and described in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP3_TABLE.

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Comparator 3

Figure 3-30 COMP3 Register

31	30	29	28	27	26	25	24
REPLACE		RESERVED	COMP
R/W-0h		R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
COMP
R/W-0h

15	14	13	12	11	10	9	8
COMP
R/W-0h

7	6	5	4	3	2	1	0
COMP						RESERVED	ENABLE
R/W-0h						R/W-0h	R/W-0h

Table 3-62 COMP3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	REPLACE	R/W	0h	This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords.
29	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28-2	COMP	R/W	0h	Comparison address.
1	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0	ENABLE	R/W	0h	Compare and remap enable comparator 3. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 3 disabled 0x1: Compare and remap for comparator 3 enabled

3.9.2.7 COMP4 Register (Offset = 18h) [Reset = 00000000h]

COMP4 is shown in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP4_FIGURE and described in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP4_TABLE.

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Comparator 4

Figure 3-31 COMP4 Register

31	30	29	28	27	26	25	24
REPLACE		RESERVED	COMP
R/W-0h		R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
COMP
R/W-0h

15	14	13	12	11	10	9	8
COMP
R/W-0h

7	6	5	4	3	2	1	0
COMP						RESERVED	ENABLE
R/W-0h						R/W-0h	R/W-0h

Table 3-63 COMP4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	REPLACE	R/W	0h	This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords.
29	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28-2	COMP	R/W	0h	Comparison address.
1	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0	ENABLE	R/W	0h	Compare and remap enable comparator 4. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 4 disabled 0x1: Compare and remap for comparator 4 enabled

3.9.2.8 COMP5 Register (Offset = 1Ch) [Reset = 00000000h]

COMP5 is shown in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP5_FIGURE and described in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP5_TABLE.

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Comparator 5

Figure 3-32 COMP5 Register

31	30	29	28	27	26	25	24
REPLACE		RESERVED	COMP
R/W-0h		R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
COMP
R/W-0h

15	14	13	12	11	10	9	8
COMP
R/W-0h

7	6	5	4	3	2	1	0
COMP						RESERVED	ENABLE
R/W-0h						R/W-0h	R/W-0h

Table 3-64 COMP5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	REPLACE	R/W	0h	This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords.
29	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28-2	COMP	R/W	0h	Comparison address.
1	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0	ENABLE	R/W	0h	Compare and remap enable comparator 5. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 5 disabled 0x1: Compare and remap for comparator 5 enabled

3.9.2.9 COMP6 Register (Offset = 20h) [Reset = 00000000h]

COMP6 is shown in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP6_FIGURE and described in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP6_TABLE.

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Comparator 6

Figure 3-33 COMP6 Register

31	30	29	28	27	26	25	24
REPLACE		RESERVED	COMP
R/W-0h		R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
COMP
R/W-0h

15	14	13	12	11	10	9	8
COMP
R/W-0h

7	6	5	4	3	2	1	0
COMP						RESERVED	ENABLE
R/W-0h						R/W-0h	R/W-0h

Table 3-65 COMP6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	REPLACE	R/W	0h	This selects what happens when the COMP address is matched. Comparator 6 is a literal comparator and the only supported setting is 0x0. Other settings will be ignored. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords.
29	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28-2	COMP	R/W	0h	Comparison address.
1	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0	ENABLE	R/W	0h	Compare and remap enable comparator 6. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 6 disabled 0x1: Compare and remap for comparator 6 enabled

3.9.2.10 COMP7 Register (Offset = 24h) [Reset = 00000000h]

COMP7 is shown in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP7_FIGURE and described in #CPU_FPB_CPU_FPB_MAP1_CPU_FPB_ALL_COMP7_TABLE.

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Comparator 7

Figure 3-34 COMP7 Register

31	30	29	28	27	26	25	24
REPLACE		RESERVED	COMP
R/W-0h		R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
COMP
R/W-0h

15	14	13	12	11	10	9	8
COMP
R/W-0h

7	6	5	4	3	2	1	0
COMP						RESERVED	ENABLE
R/W-0h						R/W-0h	R/W-0h

Table 3-66 COMP7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	REPLACE	R/W	0h	This selects what happens when the COMP address is matched. Comparator 7 is a literal comparator and the only supported setting is 0x0. Other settings will be ignored. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords.
29	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28-2	COMP	R/W	0h	Comparison address.
1	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0	ENABLE	R/W	0h	Compare and remap enable comparator 7. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 7 disabled 0x1: Compare and remap for comparator 7 enabled