SWCU192 November   2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

 

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    9.     402
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  14.   404
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    4.     448
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    5.     454
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  16.   456
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    3.     459
      1.      460
      2.      461
        1.       462
        2.       463
        3.       464
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        5.       466
      3.      467
      4.      468
    4.     469
      1.      470
      2.      471
      3.      472
      4.      473
      5.      474
    5.     475
      1.      476
  17.   477
    1.     478
    2.     479
      1.      480
      2.      481
      3.      482
        1.       483
      4.      484
    3.     485
      1.      486
      2.      487
      3.      488
    4.     489
      1.      490
  18.   491
    1.     492
    2.     493
    3.     494
    4.     495
      1.      496
  19.   497
    1.     498
    2.     499
    3.     500
    4.     501
    5.     502
      1.      503
      2.      504
      3.      505
    6.     506
      1.      507
        1.       508
        2.       509
        3.       510
          1.        511
          2.        512
    7.     513
      1.      514
  20.   515
    1.     516
      1.      517
    2.     518
      1.      519
        1.       520
      2.      521
        1.       522
        2.       523
      3.      524
      4.      525
    3.     526
      1.      527
        1.       528
        2.       529
        3.       530
        4.       531
      2.      532
        1.       533
          1.        534
        2.       535
          1.        536
          2.        537
        3.       538
          1.        539
        4.       540
          1.        541
          2.        542
          3.        543
        5.       544
        6.       545
        7.       546
        8.       547
        9.       548
        10.       549
    4.     550
      1.      551
        1.       552
      2.      553
        1.       554
        2.       555
          1.        556
          2.        557
          3.        558
          4.        559
          5.        560
      3.      561
        1.       562
        2.       563
        3.       564
      4.      565
        1.       566
        2.       567
          1.        568
          2.        569
          3.        570
      5.      571
        1.       572
        2.       573
          1.        574
          2.        575
          3.        576
          4.        577
            1.         578
            2.         579
          5.        580
          6.        581
        3.       582
          1.        583
          2.        584
          3.        585
            1.         586
            2.         587
            3.         588
            4.         589
          4.        590
      6.      591
        1.       592
        2.       593
      7.      594
        1.       595
        2.       596
          1.        597
          2.        598
          3.        599
          4.        600
          5.        601
            1.         602
              1.          603
            2.         604
              1.          605
            3.         606
              1.          607
          6.        608
    5.     609
      1.      610
        1.       611
        2.       612
      2.      613
        1.       614
        2.       615
          1.        616
          2.        617
          3.        618
          4.        619
          5.        620
          6.        621
          7.        622
          8.        623
      3.      624
        1.       625
        2.       626
          1.        627
          2.        628
          3.        629
          4.        630
      4.      631
        1.       632
        2.       633
          1.        634
          2.        635
          3.        636
            1.         637
            2.         638
      5.      639
        1.       640
        2.       641
          1.        642
          2.        643
          3.        644
            1.         645
            2.         646
            3.         647
          4.        648
            1.         649
            2.         650
            3.         651
            4.         652
          5.        653
          6.        654
      6.      655
        1.       656
        2.       657
          1.        658
          2.        659
          3.        660
          4.        661
          5.        662
    6.     663
      1.      664
        1.       665
        2.       666
          1.        667
            1.         668
            2.         669
      2.      670
      3.      671
      4.      672
      5.      673
      6.      674
      7.      675
    7.     676
    8.     677
      1.      678
      2.      679
      3.      680
      4.      681
      5.      682
      6.      683
      7.      684
      8.      685
      9.      686
      10.      687
      11.      688
      12.      689
  21.   690
    1.     691
    2.     692
    3.     693
      1.      694
  22.   695
    1.     696
    2.     697
    3.     698
    4.     699
      1.      700
      2.      701
      3.      702
      4.      703
        1.       704
        2.       705
          1.        706
          2.        707
      5.      708
      6.      709
      7.      710
    5.     711
    6.     712
    7.     713
      1.      714
  23.   715
    1.     716
    2.     717
    3.     718
    4.     719
      1.      720
      2.      721
        1.       722
        2.       723
      3.      724
      4.      725
        1.       726
        2.       727
          1.        728
          2.        729
        3.       730
        4.       731
        5.       732
        6.       733
        7.       734
    5.     735
    6.     736
    7.     737
      1.      738
  24.   739
    1.     740
    2.     741
    3.     742
      1.      743
        1.       744
        2.       745
        3.       746
        4.       747
        5.       748
      2.      749
        1.       750
      3.      751
        1.       752
        2.       753
      4.      754
      5.      755
        1.       756
        2.       757
    4.     758
    5.     759
      1.      760
  25.   761
    1.     762
    2.     763
    3.     764
    4.     765
      1.      766
        1.       767
      2.      768
      3.      769
      4.      770
        1.       771
      5.      772
        1.       773
      6.      774
        1.       775
      7.      776
        1.       777
      8.      778
        1.       779
        2.       780
    5.     781
      1.      782
      2.      783
      3.      784
      4.      785
        1.       786
        2.       787
        3.       788
    6.     789
      1.      790
      2.      791
      3.      792
      4.      793
    7.     794
    8.     795
      1.      796
      2.      797
    9.     798
      1.      799
  26.   800
    1.     801
      1.      802
    2.     803
      1.      804
      2.      805
      3.      806
        1.       807
        2.       808
        3.       809
      4.      810
        1.       811
        2.       812
        3.       813
    3.     814
      1.      815
      2.      816
        1.       817
        2.       818
        3.       819
        4.       820
        5.       821
          1.        822
          2.        823
          3.        824
        6.       825
          1.        826
        7.       827
          1.        828
          2.        829
          3.        830
          4.        831
        8.       832
      3.      833
        1.       834
          1.        835
          2.        836
          3.        837
          4.        838
          5.        839
          6.        840
          7.        841
          8.        842
          9.        843
          10.        844
          11.        845
          12.        846
          13.        847
          14.        848
        2.       849
          1.        850
          2.        851
          3.        852
          4.        853
          5.        854
          6.        855
          7.        856
          8.        857
          9.        858
          10.        859
          11.        860
          12.        861
          13.        862
          14.        863
          15.        864
          16.        865
          17.        866
          18.        867
          19.        868
          20.        869
      4.      870
        1.       871
        2.       872
        3.       873
        4.       874
        5.       875
    4.     876
      1.      877
        1.       878
        2.       879
        3.       880
        4.       881
        5.       882
      2.      883
        1.       884
        2.       885
    5.     886
      1.      887
        1.       888
        2.       889
        3.       890
        4.       891
      2.      892
      3.      893
        1.       894
        2.       895
      4.      896
        1.       897
          1.        898
            1.         899
            2.         900
          2.        901
          3.        902
          4.        903
          5.        904
        2.       905
        3.       906
        4.       907
        5.       908
        6.       909
      5.      910
        1.       911
        2.       912
        3.       913
        4.       914
        5.       915
        6.       916
    6.     917
      1.      918
        1.       919
          1.        920
        2.       921
        3.       922
        4.       923
      2.      924
    7.     925
      1.      926
      2.      927
    8.     928
      1.      929
      2.      930
      3.      931
      4.      932
      5.      933
      6.      934
      7.      935
      8.      936
        1.       937
        2.       938
        3.       939
        4.       940
      9.      941
        1.       942
        2.       943
        3.       944
      10.      945
        1.       946
        2.       947
        3.       948
        4.       949
        5.       950
      11.      951
        1.       952
        2.       953
        3.       954
        4.       955
        5.       956
      12.      957
      13.      958
      14.      959
      15.      960
      16.      961
      17.      962
    9.     963
      1.      964
    10.     965
      1.      966
      2.      967
        1.       968
          1.        969
        2.       970
        3.       971
      3.      972
      4.      973
        1.       974
        2.       975
      5.      976
        1.       977
        2.       978
          1.        979
        3.       980
          1.        981
          2.        982
        4.       983
          1.        984
          2.        985
        5.       986
          1.        987
          2.        988
          3.        989
      6.      990
        1.       991
        2.       992
    11.     993
      1.      994
      2.      995
      3.      996
  27.   997

24.5.1 I2C Registers

#I2C_I2C_MAP1_TABLE_1 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in #I2C_I2C_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 24-2 I2C Registers
Offset Acronym Register Name Section
0h SOAR Slave Own Address #I2C_I2C_MAP1_I2C_ALL_SOAR
4h SSTAT Slave Status #I2C_I2C_MAP1_I2C_ALL_SSTAT
4h SCTL Slave Control #I2C_I2C_MAP1_I2C_ALL_SCTL
8h SDR Slave Data #I2C_I2C_MAP1_I2C_ALL_SDR
Ch SIMR Slave Interrupt Mask #I2C_I2C_MAP1_I2C_ALL_SIMR
10h SRIS Slave Raw Interrupt Status #I2C_I2C_MAP1_I2C_ALL_SRIS
14h SMIS Slave Masked Interrupt Status #I2C_I2C_MAP1_I2C_ALL_SMIS
18h SICR Slave Interrupt Clear #I2C_I2C_MAP1_I2C_ALL_SICR
800h MSA Master Salve Address #I2C_I2C_MAP1_I2C_ALL_MSA
804h MSTAT Master Status #I2C_I2C_MAP1_I2C_ALL_MSTAT
804h MCTRL Master Control #I2C_I2C_MAP1_I2C_ALL_MCTRL
808h MDR Master Data #I2C_I2C_MAP1_I2C_ALL_MDR
80Ch MTPR I2C Master Timer Period #I2C_I2C_MAP1_I2C_ALL_MTPR
810h MIMR Master Interrupt Mask #I2C_I2C_MAP1_I2C_ALL_MIMR
814h MRIS Master Raw Interrupt Status #I2C_I2C_MAP1_I2C_ALL_MRIS
818h MMIS Master Masked Interrupt Status #I2C_I2C_MAP1_I2C_ALL_MMIS
81Ch MICR Master Interrupt Clear #I2C_I2C_MAP1_I2C_ALL_MICR
820h MCR Master Configuration #I2C_I2C_MAP1_I2C_ALL_MCR

Complex bit access types are encoded to fit into small table cells. #I2C_I2C_MAP1_LEGEND shows the codes that are used for access types in this section.

Table 24-3 I2C Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

24.5.1.1 SOAR Register (Offset = 0h) [Reset = 00000000h]

SOAR is shown in #I2C_I2C_MAP1_I2C_ALL_SOAR_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_SOAR_TABLE.

Return to the Summary Table.

Slave Own Address
This register consists of seven address bits that identify this I2C device on the I2C bus.

Figure 24-14 SOAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED OAR
R-0h R/W-0h
Table 24-4 SOAR Register Field Descriptions
Bit Field Type Reset Description
31-7 RESERVED R 0h Reserved
6-0 OAR R/W 0h I2C slave own address
This field specifies bits a6 through a0 of the slave address.

24.5.1.2 SSTAT Register (Offset = 4h) [Reset = 00000000h]

SSTAT is shown in #I2C_I2C_MAP1_I2C_ALL_SSTAT_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_SSTAT_TABLE.

Return to the Summary Table.

Slave Status
Note: This register shares address with SCTL, meaning that this register functions as a control register when written, and a status register when read.

Figure 24-15 SSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED FBR TREQ RREQ
R-0h R-0h R-0h R-0h
Table 24-5 SSTAT Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 FBR R 0h First byte received
0: The first byte has not been received.
1: The first byte following the slave's own address has been received.
This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the SDR register.
Note: This bit is not used for slave transmit operations.
1 TREQ R 0h Transmit request
0: No outstanding transmit request.
1: The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the SDR register.
0 RREQ R 0h Receive request
0: No outstanding receive data
1: The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until data has been read from the SDR register.

24.5.1.3 SCTL Register (Offset = 4h) [Reset = 00000000h]

SCTL is shown in #I2C_I2C_MAP1_I2C_ALL_SCTL_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_SCTL_TABLE.

Return to the Summary Table.

Slave Control
Note: This register shares address with SSTAT, meaning that this register functions as a control register when written, and a status register when read.

Figure 24-16 SCTL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DA
W-0h W-0h
Table 24-6 SCTL Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED W 0h Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior.
0 DA W 0h Device active
0: Disables the I2C slave operation
1: Enables the I2C slave operation

24.5.1.4 SDR Register (Offset = 8h) [Reset = 00000000h]

SDR is shown in #I2C_I2C_MAP1_I2C_ALL_SDR_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_SDR_TABLE.

Return to the Summary Table.

Slave Data
This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state.

Figure 24-17 SDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DATA
R-0h R/W-0h
Table 24-7 SDR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-0 DATA R/W 0h Data for transfer
This field contains the data for transfer during a slave receive or transmit operation. When written the register data is used as transmit data. When read, this register returns the last data received.
Data is stored until next update, either by a system write for transmit or by an external master for receive.

24.5.1.5 SIMR Register (Offset = Ch) [Reset = 00000000h]

SIMR is shown in #I2C_I2C_MAP1_I2C_ALL_SIMR_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_SIMR_TABLE.

Return to the Summary Table.

Slave Interrupt Mask
This register controls whether a raw interrupt is promoted to a controller interrupt.

Figure 24-18 SIMR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED STOPIM STARTIM DATAIM
R-0h R/W-0h R/W-0h R/W-0h
Table 24-8 SIMR Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 STOPIM R/W 0h Stop condition interrupt mask
0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt controller.
1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt controller.

0h = Disable Interrupt

1h = Enable Interrupt

1 STARTIM R/W 0h Start condition interrupt mask
0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt controller.
1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt controller.

0h = Disable Interrupt

1h = Enable Interrupt

0 DATAIM R/W 0h Data interrupt mask
0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt controller.
1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt controller.

24.5.1.6 SRIS Register (Offset = 10h) [Reset = 00000000h]

SRIS is shown in #I2C_I2C_MAP1_I2C_ALL_SRIS_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_SRIS_TABLE.

Return to the Summary Table.

Slave Raw Interrupt Status
This register shows the unmasked interrupt status.

Figure 24-19 SRIS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED STOPRIS STARTRIS DATARIS
R-0h R-0h R-0h R-0h
Table 24-9 SRIS Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 STOPRIS R 0h Stop condition raw interrupt status
0: No interrupt
1: A Stop condition interrupt is pending.
This bit is cleared by writing a 1 to SICR.STOPIC.
1 STARTRIS R 0h Start condition raw interrupt status
0: No interrupt
1: A Start condition interrupt is pending.
This bit is cleared by writing a 1 to SICR.STARTIC.
0 DATARIS R 0h Data raw interrupt status
0: No interrupt
1: A data received or data requested interrupt is pending.
This bit is cleared by writing a 1 to the SICR.DATAIC.

24.5.1.7 SMIS Register (Offset = 14h) [Reset = 00000000h]

SMIS is shown in #I2C_I2C_MAP1_I2C_ALL_SMIS_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_SMIS_TABLE.

Return to the Summary Table.

Slave Masked Interrupt Status
This register show which interrupt is active (based on result from SRIS and SIMR).

Figure 24-20 SMIS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED STOPMIS STARTMIS DATAMIS
R-0h R-0h R-0h R-0h
Table 24-10 SMIS Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 STOPMIS R 0h Stop condition masked interrupt status
0: An interrupt has not occurred or is masked/disabled.
1: An unmasked Stop condition interrupt is pending.
This bit is cleared by writing a 1 to the SICR.STOPIC.
1 STARTMIS R 0h Start condition masked interrupt status
0: An interrupt has not occurred or is masked/disabled.
1: An unmasked Start condition interrupt is pending.
This bit is cleared by writing a 1 to the SICR.STARTIC.
0 DATAMIS R 0h Data masked interrupt status
0: An interrupt has not occurred or is masked/disabled.
1: An unmasked data received or data requested interrupt is pending.
This bit is cleared by writing a 1 to the SICR.DATAIC.

24.5.1.8 SICR Register (Offset = 18h) [Reset = 00000000h]

SICR is shown in #I2C_I2C_MAP1_I2C_ALL_SICR_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_SICR_TABLE.

Return to the Summary Table.

Slave Interrupt Clear
This register clears the raw interrupt SRIS.

Figure 24-21 SICR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED STOPIC STARTIC DATAIC
R-0h W-0h W-0h W-0h
Table 24-11 SICR Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 STOPIC W 0h Stop condition interrupt clear
Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS.
1 STARTIC W 0h Start condition interrupt clear
Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS.
0 DATAIC W 0h Data interrupt clear
Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS.

24.5.1.9 MSA Register (Offset = 800h) [Reset = 00000000h]

MSA is shown in #I2C_I2C_MAP1_I2C_ALL_MSA_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_MSA_TABLE.

Return to the Summary Table.

Master Salve Address
This register contains seven address bits of the slave to be accessed by the master (a6-a0), and an RS bit determining if the next operation is a receive or transmit.

Figure 24-22 MSA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SA RS
R-0h R/W-0h R/W-0h
Table 24-12 MSA Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-1 SA R/W 0h I2C master slave address
Defines which slave is addressed for the transaction in master mode
0 RS R/W 0h Receive or Send
This bit-field specifies if the next operation is a receive (high) or a transmit/send (low) from the addressed slave SA.

0h = Transmit/send data to slave

1h = Receive data from slave

24.5.1.10 MSTAT Register (Offset = 804h) [Reset = 00000020h]

MSTAT is shown in #I2C_I2C_MAP1_I2C_ALL_MSTAT_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_MSTAT_TABLE.

Return to the Summary Table.

Master Status

Figure 24-23 MSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED BUSBSY IDLE ARBLST DATACK_N ADRACK_N ERR BUSY
R-0h R-0h R-1h R-0h R-0h R-0h R-0h R-0h
Table 24-13 MSTAT Register Field Descriptions
Bit Field Type Reset Description
31-7 RESERVED R 0h Reserved
6 BUSBSY R 0h Bus busy
0: The I2C bus is idle.
1: The I2C bus is busy.
The bit changes based on the MCTRL.START and MCTRL.STOP conditions.
5 IDLE R 1h I2C idle
0: The I2C controller is not idle.
1: The I2C controller is idle.
4 ARBLST R 0h Arbitration lost
0: The I2C controller won arbitration.
1: The I2C controller lost arbitration.
3 DATACK_N R 0h Data Was Not Acknowledge
0: The transmitted data was acknowledged.
1: The transmitted data was not acknowledged.
2 ADRACK_N R 0h Address Was Not Acknowledge
0: The transmitted address was acknowledged.
1: The transmitted address was not acknowledged.
1 ERR R 0h Error
0: No error was detected on the last operation.
1: An error occurred on the last operation.
0 BUSY R 0h I2C busy
0: The controller is idle.
1: The controller is busy.
When this bit-field is set, the other status bits are not valid.
Note: The I2C controller requires four SYSBUS clock cycles to assert the BUSY status after I2C master operation has been initiated through MCTRL register.
Hence after programming MCTRL register, application is requested to wait for four SYSBUS clock cycles before issuing a controller status inquiry through MSTAT register.
Any prior inquiry would result in wrong status being reported.

24.5.1.11 MCTRL Register (Offset = 804h) [Reset = 00000000h]

MCTRL is shown in #I2C_I2C_MAP1_I2C_ALL_MCTRL_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_MCTRL_TABLE.

Return to the Summary Table.

Master Control
This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller as stated in MSTAT. When written, the control register configures the I2C controller operation.
To generate a single transmit cycle, the I2C Master Slave Address (MSA) register is written with the desired address, the MSA.RS bit is cleared, and this register is written with
* ACK=X (0 or 1),
* STOP=1,
* START=1,
* RUN=1
to perform the operation and stop.
When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the MDR register.

Figure 24-24 MCTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ACK STOP START RUN
R-0h W-0h W-0h W-0h W-0h
Table 24-14 MCTRL Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3 ACK W 0h Data acknowledge enable
0: The received data byte is not acknowledged automatically by the master.
1: The received data byte is acknowledged automatically by the master.
This bit-field must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter.

0h = Disable acknowledge

1h = Enable acknowledge

2 STOP W 0h This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition.
0: The controller does not generate the Stop condition.
1: The controller generates the Stop condition.

0h = Disable STOP

1h = Enable STOP

1 START W 0h This bit-field generates the Start or Repeated Start condition.
0: The controller does not generate the Start condition.
1: The controller generates the Start condition.

0h = Disable START

1h = Enable START

0 RUN W 0h I2C master enable
0: The master is disabled.
1: The master is enabled to transmit or receive data.

0h = Disable Master

1h = Enable Master

24.5.1.12 MDR Register (Offset = 808h) [Reset = 00000000h]

MDR is shown in #I2C_I2C_MAP1_I2C_ALL_MDR_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_MDR_TABLE.

Return to the Summary Table.

Master Data
This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state.

Figure 24-25 MDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DATA
R-0h R/W-0h
Table 24-15 MDR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-0 DATA R/W 0h When Read: Last RX Data is returned
When Written: Data is transferred during TX transaction

24.5.1.13 MTPR Register (Offset = 80Ch) [Reset = 00000001h]

MTPR is shown in #I2C_I2C_MAP1_I2C_ALL_MTPR_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_MTPR_TABLE.

Return to the Summary Table.

I2C Master Timer Period
This register specifies the period of the SCL clock.

Figure 24-26 MTPR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
TPR_7 TPR
R/W-0h R/W-1h
Table 24-16 MTPR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7 TPR_7 R/W 0h Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored.
6-0 TPR R/W 1h SCL clock period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the timer period register value (range of 1 to 127)
SCL_LP is the SCL low period (fixed at 6).
SCL_HP is the SCL high period (fixed at 4).
CLK_PRD is the system clock period in ns.

24.5.1.14 MIMR Register (Offset = 810h) [Reset = 00000000h]

MIMR is shown in #I2C_I2C_MAP1_I2C_ALL_MIMR_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_MIMR_TABLE.

Return to the Summary Table.

Master Interrupt Mask
This register controls whether a raw interrupt is promoted to a controller interrupt.

Figure 24-27 MIMR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED IM
R-0h R/W-0h
Table 24-17 MIMR Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 IM R/W 0h Interrupt mask
0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt controller.
1: The master interrupt is sent to the interrupt controller when the MRIS.RIS is set.

0h = Disable Interrupt

1h = Enable Interrupt

24.5.1.15 MRIS Register (Offset = 814h) [Reset = 00000000h]

MRIS is shown in #I2C_I2C_MAP1_I2C_ALL_MRIS_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_MRIS_TABLE.

Return to the Summary Table.

Master Raw Interrupt Status
This register show the unmasked interrupt status.

Figure 24-28 MRIS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RIS
R-0h R-0h
Table 24-18 MRIS Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 RIS R 0h Raw interrupt status
0: No interrupt
1: A master interrupt is pending.
This bit is cleared by writing 1 to the MICR.IC bit .

24.5.1.16 MMIS Register (Offset = 818h) [Reset = 00000000h]

MMIS is shown in #I2C_I2C_MAP1_I2C_ALL_MMIS_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_MMIS_TABLE.

Return to the Summary Table.

Master Masked Interrupt Status
This register show which interrupt is active (based on result from MRIS and MIMR).

Figure 24-29 MMIS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MIS
R-0h R-0h
Table 24-19 MMIS Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 MIS R 0h Masked interrupt status
0: An interrupt has not occurred or is masked.
1: A master interrupt is pending.
This bit is cleared by writing 1 to the MICR.IC bit .

24.5.1.17 MICR Register (Offset = 81Ch) [Reset = 00000000h]

MICR is shown in #I2C_I2C_MAP1_I2C_ALL_MICR_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_MICR_TABLE.

Return to the Summary Table.

Master Interrupt Clear
This register clears the raw and masked interrupt.

Figure 24-30 MICR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED IC
R-0h W-0h
Table 24-20 MICR Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 IC W 0h Interrupt clear
Writing 1 to this bit clears MRIS.RIS and MMIS.MIS .
Reading this register returns no meaningful data.

24.5.1.18 MCR Register (Offset = 820h) [Reset = 00000000h]

MCR is shown in #I2C_I2C_MAP1_I2C_ALL_MCR_FIGURE and described in #I2C_I2C_MAP1_I2C_ALL_MCR_TABLE.

Return to the Summary Table.

Master Configuration
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.

Figure 24-31 MCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SFE MFE RESERVED LPBK
R-0h R/W-0h R/W-0h R-0h R/W-0h
Table 24-21 MCR Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5 SFE R/W 0h I2C slave function enable

0h = Slave mode is disabled.

1h = Slave mode is enabled.

4 MFE R/W 0h I2C master function enable

0h = Master mode is disabled.

1h = Master mode is enabled.

3-1 RESERVED R 0h Reserved
0 LPBK R/W 0h I2C loopback
0: Normal operation
1: Loopback operation (test mode)

0h = Disable Test Mode

1h = Enable Test Mode