SWCU192 November   2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

 

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    9.     402
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  14.   404
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    4.     448
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    5.     454
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  16.   456
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    3.     459
      1.      460
      2.      461
        1.       462
        2.       463
        3.       464
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        5.       466
      3.      467
      4.      468
    4.     469
      1.      470
      2.      471
      3.      472
      4.      473
      5.      474
    5.     475
      1.      476
  17.   477
    1.     478
    2.     479
      1.      480
      2.      481
      3.      482
        1.       483
      4.      484
    3.     485
      1.      486
      2.      487
      3.      488
    4.     489
      1.      490
  18.   491
    1.     492
    2.     493
    3.     494
    4.     495
      1.      496
  19.   497
    1.     498
    2.     499
    3.     500
    4.     501
    5.     502
      1.      503
      2.      504
      3.      505
    6.     506
      1.      507
        1.       508
        2.       509
        3.       510
          1.        511
          2.        512
    7.     513
      1.      514
  20.   515
    1.     516
      1.      517
    2.     518
      1.      519
        1.       520
      2.      521
        1.       522
        2.       523
      3.      524
      4.      525
    3.     526
      1.      527
        1.       528
        2.       529
        3.       530
        4.       531
      2.      532
        1.       533
          1.        534
        2.       535
          1.        536
          2.        537
        3.       538
          1.        539
        4.       540
          1.        541
          2.        542
          3.        543
        5.       544
        6.       545
        7.       546
        8.       547
        9.       548
        10.       549
    4.     550
      1.      551
        1.       552
      2.      553
        1.       554
        2.       555
          1.        556
          2.        557
          3.        558
          4.        559
          5.        560
      3.      561
        1.       562
        2.       563
        3.       564
      4.      565
        1.       566
        2.       567
          1.        568
          2.        569
          3.        570
      5.      571
        1.       572
        2.       573
          1.        574
          2.        575
          3.        576
          4.        577
            1.         578
            2.         579
          5.        580
          6.        581
        3.       582
          1.        583
          2.        584
          3.        585
            1.         586
            2.         587
            3.         588
            4.         589
          4.        590
      6.      591
        1.       592
        2.       593
      7.      594
        1.       595
        2.       596
          1.        597
          2.        598
          3.        599
          4.        600
          5.        601
            1.         602
              1.          603
            2.         604
              1.          605
            3.         606
              1.          607
          6.        608
    5.     609
      1.      610
        1.       611
        2.       612
      2.      613
        1.       614
        2.       615
          1.        616
          2.        617
          3.        618
          4.        619
          5.        620
          6.        621
          7.        622
          8.        623
      3.      624
        1.       625
        2.       626
          1.        627
          2.        628
          3.        629
          4.        630
      4.      631
        1.       632
        2.       633
          1.        634
          2.        635
          3.        636
            1.         637
            2.         638
      5.      639
        1.       640
        2.       641
          1.        642
          2.        643
          3.        644
            1.         645
            2.         646
            3.         647
          4.        648
            1.         649
            2.         650
            3.         651
            4.         652
          5.        653
          6.        654
      6.      655
        1.       656
        2.       657
          1.        658
          2.        659
          3.        660
          4.        661
          5.        662
    6.     663
      1.      664
        1.       665
        2.       666
          1.        667
            1.         668
            2.         669
      2.      670
      3.      671
      4.      672
      5.      673
      6.      674
      7.      675
    7.     676
    8.     677
      1.      678
      2.      679
      3.      680
      4.      681
      5.      682
      6.      683
      7.      684
      8.      685
      9.      686
      10.      687
      11.      688
      12.      689
  21.   690
    1.     691
    2.     692
    3.     693
      1.      694
  22.   695
    1.     696
    2.     697
    3.     698
    4.     699
      1.      700
      2.      701
      3.      702
      4.      703
        1.       704
        2.       705
          1.        706
          2.        707
      5.      708
      6.      709
      7.      710
    5.     711
    6.     712
    7.     713
      1.      714
  23.   715
    1.     716
    2.     717
    3.     718
    4.     719
      1.      720
      2.      721
        1.       722
        2.       723
      3.      724
      4.      725
        1.       726
        2.       727
          1.        728
          2.        729
        3.       730
        4.       731
        5.       732
        6.       733
        7.       734
    5.     735
    6.     736
    7.     737
      1.      738
  24.   739
    1.     740
    2.     741
    3.     742
      1.      743
        1.       744
        2.       745
        3.       746
        4.       747
        5.       748
      2.      749
        1.       750
      3.      751
        1.       752
        2.       753
      4.      754
      5.      755
        1.       756
        2.       757
    4.     758
    5.     759
      1.      760
  25.   761
    1.     762
    2.     763
    3.     764
    4.     765
      1.      766
        1.       767
      2.      768
      3.      769
      4.      770
        1.       771
      5.      772
        1.       773
      6.      774
        1.       775
      7.      776
        1.       777
      8.      778
        1.       779
        2.       780
    5.     781
      1.      782
      2.      783
      3.      784
      4.      785
        1.       786
        2.       787
        3.       788
    6.     789
      1.      790
      2.      791
      3.      792
      4.      793
    7.     794
    8.     795
      1.      796
      2.      797
    9.     798
      1.      799
  26.   800
    1.     801
      1.      802
    2.     803
      1.      804
      2.      805
      3.      806
        1.       807
        2.       808
        3.       809
      4.      810
        1.       811
        2.       812
        3.       813
    3.     814
      1.      815
      2.      816
        1.       817
        2.       818
        3.       819
        4.       820
        5.       821
          1.        822
          2.        823
          3.        824
        6.       825
          1.        826
        7.       827
          1.        828
          2.        829
          3.        830
          4.        831
        8.       832
      3.      833
        1.       834
          1.        835
          2.        836
          3.        837
          4.        838
          5.        839
          6.        840
          7.        841
          8.        842
          9.        843
          10.        844
          11.        845
          12.        846
          13.        847
          14.        848
        2.       849
          1.        850
          2.        851
          3.        852
          4.        853
          5.        854
          6.        855
          7.        856
          8.        857
          9.        858
          10.        859
          11.        860
          12.        861
          13.        862
          14.        863
          15.        864
          16.        865
          17.        866
          18.        867
          19.        868
          20.        869
      4.      870
        1.       871
        2.       872
        3.       873
        4.       874
        5.       875
    4.     876
      1.      877
        1.       878
        2.       879
        3.       880
        4.       881
        5.       882
      2.      883
        1.       884
        2.       885
    5.     886
      1.      887
        1.       888
        2.       889
        3.       890
        4.       891
      2.      892
      3.      893
        1.       894
        2.       895
      4.      896
        1.       897
          1.        898
            1.         899
            2.         900
          2.        901
          3.        902
          4.        903
          5.        904
        2.       905
        3.       906
        4.       907
        5.       908
        6.       909
      5.      910
        1.       911
        2.       912
        3.       913
        4.       914
        5.       915
        6.       916
    6.     917
      1.      918
        1.       919
          1.        920
        2.       921
        3.       922
        4.       923
      2.      924
    7.     925
      1.      926
      2.      927
    8.     928
      1.      929
      2.      930
      3.      931
      4.      932
      5.      933
      6.      934
      7.      935
      8.      936
        1.       937
        2.       938
        3.       939
        4.       940
      9.      941
        1.       942
        2.       943
        3.       944
      10.      945
        1.       946
        2.       947
        3.       948
        4.       949
        5.       950
      11.      951
        1.       952
        2.       953
        3.       954
        4.       955
        5.       956
      12.      957
      13.      958
      14.      959
      15.      960
      16.      961
      17.      962
    9.     963
      1.      964
    10.     965
      1.      966
      2.      967
        1.       968
          1.        969
        2.       970
        3.       971
      3.      972
      4.      973
        1.       974
        2.       975
      5.      976
        1.       977
        2.       978
          1.        979
        3.       980
          1.        981
          2.        982
        4.       983
          1.        984
          2.        985
        5.       986
          1.        987
          2.        988
          3.        989
      6.      990
        1.       991
        2.       992
    11.     993
      1.      994
      2.      995
      3.      996
  27.   997

12.2.1 CCFG Registers

#CCFG_CCFG_MMAP1_TABLE_1 lists the memory-mapped registers for the CCFG registers. All register offset addresses not listed in #CCFG_CCFG_MMAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 12-1 CCFG Registers
OffsetAcronymRegister NameSection
1FA8hEXT_LF_CLKExtern LF clock configuration#CCFG_CCFG_MMAP1_CCFG_ALL_EXT_LF_CLK
1FAChMODE_CONF_1Mode Configuration 1#CCFG_CCFG_MMAP1_CCFG_ALL_MODE_CONF_1
1FB0hSIZE_AND_DIS_FLAGSCCFG Size and Disable Flags#CCFG_CCFG_MMAP1_CCFG_ALL_SIZE_AND_DIS_FLAGS
1FB4hMODE_CONFMode Configuration 0#CCFG_CCFG_MMAP1_CCFG_ALL_MODE_CONF
1FB8hVOLT_LOAD_0Voltage Load 0#CCFG_CCFG_MMAP1_CCFG_ALL_VOLT_LOAD_0
1FBChVOLT_LOAD_1Voltage Load 1#CCFG_CCFG_MMAP1_CCFG_ALL_VOLT_LOAD_1
1FC0hRTC_OFFSETReal Time Clock Offset#CCFG_CCFG_MMAP1_CCFG_ALL_RTC_OFFSET
1FC4hFREQ_OFFSETFrequency Offset#CCFG_CCFG_MMAP1_CCFG_ALL_FREQ_OFFSET
1FC8hIEEE_MAC_0IEEE MAC Address 0#CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_MAC_0
1FCChIEEE_MAC_1IEEE MAC Address 1#CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_MAC_1
1FD0hIEEE_BLE_0IEEE BLE Address 0#CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_BLE_0
1FD4hIEEE_BLE_1IEEE BLE Address 1#CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_BLE_1
1FD8hBL_CONFIGBootloader Configuration#CCFG_CCFG_MMAP1_CCFG_ALL_BL_CONFIG
1FDChERASE_CONFErase Configuration#CCFG_CCFG_MMAP1_CCFG_ALL_ERASE_CONF
1FE0hCCFG_TI_OPTIONSTI Options#CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_TI_OPTIONS
1FE4hCCFG_TAP_DAP_0Test Access Points Enable 0#CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_TAP_DAP_0
1FE8hCCFG_TAP_DAP_1Test Access Points Enable 1#CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_TAP_DAP_1
1FEChIMAGE_VALID_CONFImage Valid#CCFG_CCFG_MMAP1_CCFG_ALL_IMAGE_VALID_CONF
1FF0hCCFG_PROT_31_0Protect Sectors 0-31#CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_31_0
1FF4hCCFG_PROT_63_32Protect Sectors 32-63#CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_63_32
1FF8hCCFG_PROT_95_64Protect Sectors 64-95#CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_95_64
1FFChCCFG_PROT_127_96Protect Sectors 96-127#CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_127_96

Complex bit access types are encoded to fit into small table cells. #CCFG_CCFG_MMAP1_LEGEND shows the codes that are used for access types in this section.

Table 12-2 CCFG Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

12.2.1.1 EXT_LF_CLK Register (Offset = 1FA8h) [Reset = FFFFFFFFh]

EXT_LF_CLK is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_EXT_LF_CLK_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_EXT_LF_CLK_TABLE.

Return to the Summary Table.

Extern LF clock configuration

Figure 12-1 EXT_LF_CLK Register
313029282726252423222120191817161514131211109876543210
DIORTC_INCREMENT
R-FFhR-00FFFFFFh
Table 12-3 EXT_LF_CLK Register Field Descriptions
BitFieldTypeResetDescription
31-24DIORFFhUnsigned integer, selecting the DIO to supply external 32kHz clock as SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO will be marked as reserved by the pin driver (TI-RTOS environment) and hence not selectable for other usage.
23-0RTC_INCREMENTR00FFFFFFhUnsigned integer, defining the input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: EXT_LF_CLK.RTC_INCREMENT = 238/InputClockFrequency in Hertz (e.g.: RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz)

12.2.1.2 MODE_CONF_1 Register (Offset = 1FACh) [Reset = FFFFFFFFh]

MODE_CONF_1 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_MODE_CONF_1_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_MODE_CONF_1_TABLE.

Return to the Summary Table.

Mode Configuration 1

Figure 12-2 MODE_CONF_1 Register
3130292827262524
TCXO_TYPETCXO_MAX_START
R-1hR-7Fh
2322212019181716
ALT_DCDC_VMINALT_DCDC_DITHER_ENALT_DCDC_IPEAK
R-FhR-1hR-7h
15141312111098
DELTA_IBIAS_INITDELTA_IBIAS_OFFSET
R-FhR-Fh
76543210
XOSC_MAX_START
R-FFh
Table 12-4 MODE_CONF_1 Register Field Descriptions
BitFieldTypeResetDescription
31TCXO_TYPER1hSelects the TCXO type.
0: CMOS type. Internal common-mode bias will not be enabled.
1: Clipped-sine type. Internal common-mode bias will be enabled when TCXO is used.
Bit field value is only valid if MODE_CONF.XOSC_FREQ=0.
30-24TCXO_MAX_STARTR7FhMaximum TCXO startup time in units of 100us.
Bit field value is only valid if MODE_CONF.XOSC_FREQ=0.
23-20ALT_DCDC_VMINRFhMinimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).
Voltage = (28 + ALT_DCDC_VMIN) / 16.
0: 1.75V
1: 1.8125V
...
14: 2.625V
15: 2.6875V
NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!).
19ALT_DCDC_DITHER_ENR1hEnable DC/DC dithering if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).
0: Dither disable
1: Dither enable
18-16ALT_DCDC_IPEAKR7hInductor peak current if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external inductor!
0: 46mA (min)
...
4: 70mA
...
7: 87mA (max)
15-12DELTA_IBIAS_INITRFhSigned delta value for IBIAS_INIT. Delta value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.
See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT
11-8DELTA_IBIAS_OFFSETRFhSigned delta value for IBIAS_OFFSET. Delta value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.
See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET
7-0XOSC_MAX_STARTRFFhUnsigned value of maximum XOSC startup time (worst case) in units of 100us. Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.

12.2.1.3 SIZE_AND_DIS_FLAGS Register (Offset = 1FB0h) [Reset = FFFFFFFFh]

SIZE_AND_DIS_FLAGS is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_SIZE_AND_DIS_FLAGS_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_SIZE_AND_DIS_FLAGS_TABLE.

Return to the Summary Table.

CCFG Size and Disable Flags

Figure 12-3 SIZE_AND_DIS_FLAGS Register
3130292827262524
SIZE_OF_CCFG
R-FFFFh
2322212019181716
SIZE_OF_CCFG
R-FFFFh
15141312111098
DISABLE_FLAGS
R-FFFh
76543210
DISABLE_FLAGSDIS_TCXODIS_GPRAMDIS_ALT_DCDC_SETTINGDIS_XOSC_OVR
R-FFFhR-1hR-1hR-1hR-1h
Table 12-5 SIZE_AND_DIS_FLAGS Register Field Descriptions
BitFieldTypeResetDescription
31-16SIZE_OF_CCFGRFFFFhTotal size of CCFG in bytes.
15-4DISABLE_FLAGSRFFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
3DIS_TCXOR1hDeprecated. Must be set to 1.
2DIS_GPRAMR1hDisable GPRAM (or use the 8K VIMS RAM as CACHE RAM).
0: GPRAM is enabled and hence CACHE disabled.
1: GPRAM is disabled and instead CACHE is enabled (default).
Notes:
- Disabling CACHE will reduce CPU execution speed (up to 60%).
- GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if enabled.
See:
VIMS:CTL.MODE
1DIS_ALT_DCDC_SETTINGR1hDisable alternate DC/DC settings.
0: Enable alternate DC/DC settings.
1: Disable alternate DC/DC settings.
See:
MODE_CONF_1.ALT_DCDC_VMIN
MODE_CONF_1.ALT_DCDC_DITHER_EN
MODE_CONF_1.ALT_DCDC_IPEAK
NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!).
0DIS_XOSC_OVRR1hDisable XOSC override functionality.
0: Enable XOSC override functionality.
1: Disable XOSC override functionality.
See:
MODE_CONF_1.DELTA_IBIAS_INIT
MODE_CONF_1.DELTA_IBIAS_OFFSET
MODE_CONF_1.XOSC_MAX_START

12.2.1.4 MODE_CONF Register (Offset = 1FB4h) [Reset = FFFFFFFFh]

MODE_CONF is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_MODE_CONF_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_MODE_CONF_TABLE.

Return to the Summary Table.

Mode Configuration 0

Figure 12-4 MODE_CONF Register
3130292827262524
VDDR_TRIM_SLEEP_DELTADCDC_RECHARGEDCDC_ACTIVEVDDR_EXT_LOADVDDS_BOD_LEVEL
R-FhR-1hR-1hR-1hR-1h
2322212019181716
SCLK_LF_OPTIONVDDR_TRIM_SLEEP_TCRTC_COMPXOSC_FREQXOSC_CAP_MODHF_COMP
R-3hR-1hR-1hR-3hR-1hR-1h
15141312111098
XOSC_CAPARRAY_DELTA
R-FFh
76543210
VDDR_CAP
R-FFh
Table 12-6 MODE_CONF Register Field Descriptions
BitFieldTypeResetDescription
31-28VDDR_TRIM_SLEEP_DELTARFhSigned delta value to apply to the
VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H.
0x8 (-8) : Delta = -7
...
0xF (-1) : Delta = 0
0x0 (0) : Delta = +1
...
0x7 (7) : Delta = +8
27DCDC_RECHARGER1hDC/DC during recharge in powerdown.
0: Use the DC/DC during recharge in powerdown.
1: Do not use the DC/DC during recharge in powerdown (default).
NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!).
26DCDC_ACTIVER1hDC/DC in active mode.
0: Use the DC/DC during active mode.
1: Do not use the DC/DC during active mode (default).
NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!).
25VDDR_EXT_LOADR1hReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
24VDDS_BOD_LEVELR1hVDDS BOD level.
0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum PA output power on CC13xx).
1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default).
23-22SCLK_LF_OPTIONR3hSelect source for SCLK_LF.

0h = 31.25kHz clock derived from 48MHz XOSC. The RTC tick speed AON_RTC:SUBSECINC is updated to 0x8637BD, corresponding to a 31.25kHz clock (done in the SetupTrimDevice() driverlib boot function). The device must be blocked from entering Standby mode when using this clock source.

1h = External low frequency clock on DIO defined by EXT_LF_CLK.DIO. The RTC tick speed AON_RTC:SUBSECINC is updated to EXT_LF_CLK.RTC_INCREMENT (done in the SetupTrimDevice() driverlib boot function). External clock must always be running when the chip is in standby for VDDR recharge timing.

2h = 32.768kHz low frequency XOSC

3h = Low frequency RCOSC (default)

21VDDR_TRIM_SLEEP_TCR1h0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated
0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time standby mode is entered. This improves low-temperature RCOSC_LF frequency stability in standby mode.
When temperature compensation is performed, the delta is calculates this way:
Delta = max (delta, min(8, floor(62-temp)/8))
Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current temperature in degrees C.
20RTC_COMPR1hReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
19-18XOSC_FREQR3hSelects which high frequency oscillator is used (required for radio usage).

0h = External 48Mhz TCXO.
Refer to MODE_CONF_1.TCXO_MAX_START and MODE_CONF_1.TCXO_TYPE bit fields for additional configuration of TCXO.

1h = Internal high precision oscillator.

2h = 48M : 48 MHz XOSC_HF

3h = 24M : 24 MHz XOSC_HF. Not supported.

17XOSC_CAP_MODR1hEnable modification (delta) to XOSC cap-array. Value specified in XOSC_CAPARRAY_DELTA.
0: Apply cap-array delta
1: Do not apply cap-array delta (default)
16HF_COMPR1hReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
15-8XOSC_CAPARRAY_DELTARFFhSigned 8-bit value, directly modifying trimmed XOSC cap-array step value. Enabled by XOSC_CAP_MOD.
7-0VDDR_CAPRFFhUnsigned 8-bit integer, representing the minimum decoupling capacitance (worst case) on VDDR, in units of 100nF. This should take into account capacitor tolerance and voltage dependent capacitance variation. This bit affects the recharge period calculation when going into powerdown or standby.

NOTE! If using the following functions this field must be configured (used by TI RTOS):
SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown()

12.2.1.5 VOLT_LOAD_0 Register (Offset = 1FB8h) [Reset = FFFFFFFFh]

VOLT_LOAD_0 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_VOLT_LOAD_0_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_VOLT_LOAD_0_TABLE.

Return to the Summary Table.

Voltage Load 0
Enabled by MODE_CONF.VDDR_EXT_LOAD.

Figure 12-5 VOLT_LOAD_0 Register
31302928272625242322212019181716
VDDR_EXT_TP45VDDR_EXT_TP25
R-FFhR-FFh
1514131211109876543210
VDDR_EXT_TP5VDDR_EXT_TM15
R-FFhR-FFh
Table 12-7 VOLT_LOAD_0 Register Field Descriptions
BitFieldTypeResetDescription
31-24VDDR_EXT_TP45RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
23-16VDDR_EXT_TP25RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
15-8VDDR_EXT_TP5RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
7-0VDDR_EXT_TM15RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.

12.2.1.6 VOLT_LOAD_1 Register (Offset = 1FBCh) [Reset = FFFFFFFFh]

VOLT_LOAD_1 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_VOLT_LOAD_1_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_VOLT_LOAD_1_TABLE.

Return to the Summary Table.

Voltage Load 1
Enabled by MODE_CONF.VDDR_EXT_LOAD.

Figure 12-6 VOLT_LOAD_1 Register
31302928272625242322212019181716
VDDR_EXT_TP125VDDR_EXT_TP105
R-FFhR-FFh
1514131211109876543210
VDDR_EXT_TP85VDDR_EXT_TP65
R-FFhR-FFh
Table 12-8 VOLT_LOAD_1 Register Field Descriptions
BitFieldTypeResetDescription
31-24VDDR_EXT_TP125RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
23-16VDDR_EXT_TP105RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
15-8VDDR_EXT_TP85RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
7-0VDDR_EXT_TP65RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.

12.2.1.7 RTC_OFFSET Register (Offset = 1FC0h) [Reset = FFFFFFFFh]

RTC_OFFSET is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_RTC_OFFSET_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_RTC_OFFSET_TABLE.

Return to the Summary Table.

Real Time Clock Offset
Enabled by MODE_CONF.RTC_COMP.

Figure 12-7 RTC_OFFSET Register
31302928272625242322212019181716
RTC_COMP_P0
R-FFFFh
1514131211109876543210
RTC_COMP_P1RTC_COMP_P2
R-FFhR-FFh
Table 12-9 RTC_OFFSET Register Field Descriptions
BitFieldTypeResetDescription
31-16RTC_COMP_P0RFFFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
15-8RTC_COMP_P1RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
7-0RTC_COMP_P2RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.

12.2.1.8 FREQ_OFFSET Register (Offset = 1FC4h) [Reset = FFFFFFFFh]

FREQ_OFFSET is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_FREQ_OFFSET_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_FREQ_OFFSET_TABLE.

Return to the Summary Table.

Frequency Offset

Figure 12-8 FREQ_OFFSET Register
31302928272625242322212019181716
HF_COMP_P0
R-FFFFh
1514131211109876543210
HF_COMP_P1HF_COMP_P2
R-FFhR-FFh
Table 12-10 FREQ_OFFSET Register Field Descriptions
BitFieldTypeResetDescription
31-16HF_COMP_P0RFFFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
15-8HF_COMP_P1RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
7-0HF_COMP_P2RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.

12.2.1.9 IEEE_MAC_0 Register (Offset = 1FC8h) [Reset = FFFFFFFFh]

IEEE_MAC_0 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_MAC_0_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_MAC_0_TABLE.

Return to the Summary Table.

IEEE MAC Address 0

Figure 12-9 IEEE_MAC_0 Register
313029282726252423222120191817161514131211109876543210
ADDR
R-FFFFFFFFh
Table 12-11 IEEE_MAC_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRRFFFFFFFFhBits[31:0] of the 64-bits custom IEEE MAC address.
If different from 0xFFFFFFFF then the value of this field is applied
otherwise use value from FCFG.

12.2.1.10 IEEE_MAC_1 Register (Offset = 1FCCh) [Reset = FFFFFFFFh]

IEEE_MAC_1 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_MAC_1_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_MAC_1_TABLE.

Return to the Summary Table.

IEEE MAC Address 1

Figure 12-10 IEEE_MAC_1 Register
313029282726252423222120191817161514131211109876543210
ADDR
R-FFFFFFFFh
Table 12-12 IEEE_MAC_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRRFFFFFFFFhBits[63:32] of the 64-bits custom IEEE MAC address.
If different from 0xFFFFFFFF then the value of this field is applied
otherwise use value from FCFG.

12.2.1.11 IEEE_BLE_0 Register (Offset = 1FD0h) [Reset = FFFFFFFFh]

IEEE_BLE_0 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_BLE_0_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_BLE_0_TABLE.

Return to the Summary Table.

IEEE BLE Address 0

Figure 12-11 IEEE_BLE_0 Register
313029282726252423222120191817161514131211109876543210
ADDR
R-FFFFFFFFh
Table 12-13 IEEE_BLE_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRRFFFFFFFFhBits[31:0] of the 64-bits custom IEEE BLE address.
If different from 0xFFFFFFFF then the value of this field is applied
otherwise use value from FCFG.

12.2.1.12 IEEE_BLE_1 Register (Offset = 1FD4h) [Reset = FFFFFFFFh]

IEEE_BLE_1 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_BLE_1_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_IEEE_BLE_1_TABLE.

Return to the Summary Table.

IEEE BLE Address 1

Figure 12-12 IEEE_BLE_1 Register
313029282726252423222120191817161514131211109876543210
ADDR
R-FFFFFFFFh
Table 12-14 IEEE_BLE_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRRFFFFFFFFhBits[63:32] of the 64-bits custom IEEE BLE address.
If different from 0xFFFFFFFF then the value of this field is applied
otherwise use value from FCFG.

12.2.1.13 BL_CONFIG Register (Offset = 1FD8h) [Reset = C5FFFFFFh]

BL_CONFIG is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_BL_CONFIG_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_BL_CONFIG_TABLE.

Return to the Summary Table.

Bootloader Configuration
Configures the functionality of the ROM boot loader.
If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is enabled by the BL_ENABLE field it is possible to force entry of the ROM boot loader even if a valid image is present in flash.

Figure 12-13 BL_CONFIG Register
3130292827262524
BOOTLOADER_ENABLE
R-C5h
2322212019181716
RESERVEDBL_LEVEL
R-0hR-1h
15141312111098
BL_PIN_NUMBER
R-FFh
76543210
BL_ENABLE
R-FFh
Table 12-15 BL_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-24BOOTLOADER_ENABLERC5hBootloader enable. Boot loader can be accessed if IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and conditions for boot loader backdoor are met).
0xC5: Boot loader is enabled.
Any other value: Boot loader is disabled.
23-17RESERVEDR0hReserved
16BL_LEVELR1hSets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field.
0: Active low.
1: Active high.
15-8BL_PIN_NUMBERRFFhDIO number that is level checked if the boot loader backdoor is enabled by the BL_ENABLE field.
7-0BL_ENABLERFFhEnables the boot loader backdoor.
0xC5: Boot loader backdoor is enabled.
Any other value: Boot loader backdoor is disabled.
NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader backdoor is enabled.

12.2.1.14 ERASE_CONF Register (Offset = 1FDCh) [Reset = FFFFFFFFh]

ERASE_CONF is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_ERASE_CONF_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_ERASE_CONF_TABLE.

Return to the Summary Table.

Erase Configuration

Figure 12-14 ERASE_CONF Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCHIP_ERASE_DIS_N
R-0hR-1h
76543210
RESERVEDBANK_ERASE_DIS_N
R-0hR-1h
Table 12-16 ERASE_CONF Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8CHIP_ERASE_DIS_NR1hChip erase.
This bit controls if a chip erase requested through the JTAG WUC TAP will be ignored in a following boot caused by a reset of the MCU VD.
A successful chip erase operation will force the content of the flash main bank back to the state as it was when delivered by TI.
0: Disable. Any chip erase request detected during boot will be ignored.
1: Enable. Any chip erase request detected during boot will be performed by the boot FW.
7-1RESERVEDR0hReserved
0BANK_ERASE_DIS_NR1hBank erase.
This bit controls if the ROM serial boot loader will accept a received Bank Erase command (COMMAND_BANK_ERASE).
A successful Bank Erase operation will erase all main bank sectors not protected by write protect configuration bits in CCFG.
0: Disable the boot loader bank erase function.
1: Enable the boot loader bank erase function.

12.2.1.15 CCFG_TI_OPTIONS Register (Offset = 1FE0h) [Reset = FFFFFFC5h]

CCFG_TI_OPTIONS is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_TI_OPTIONS_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_TI_OPTIONS_TABLE.

Return to the Summary Table.

TI Options

Figure 12-15 CCFG_TI_OPTIONS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDTI_FA_ENABLE
R-0hR-C5h
Table 12-17 CCFG_TI_OPTIONS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0TI_FA_ENABLERC5hTI Failure Analysis.
0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) option with the unlock code.
All other values: Disable the functionality of unlocking the TI FA option with the unlock code.

12.2.1.16 CCFG_TAP_DAP_0 Register (Offset = 1FE4h) [Reset = FFC5C5C5h]

CCFG_TAP_DAP_0 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_TAP_DAP_0_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_TAP_DAP_0_TABLE.

Return to the Summary Table.

Test Access Points Enable 0

Figure 12-16 CCFG_TAP_DAP_0 Register
31302928272625242322212019181716
RESERVEDCPU_DAP_ENABLE
R-0hR-C5h
1514131211109876543210
PWRPROF_TAP_ENABLETEST_TAP_ENABLE
R-C5hR-C5h
Table 12-18 CCFG_TAP_DAP_0 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16CPU_DAP_ENABLERC5hEnable CPU DAP.
0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM boot FW.
Any other value: Main CPU DAP access will remain disabled out of power-up/system-reset.
15-8PWRPROF_TAP_ENABLERC5hEnable PWRPROF TAP.
0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.
Any other value: PWRPROF TAP access will remain disabled out of power-up/system-reset.
7-0TEST_TAP_ENABLERC5hEnable Test TAP.
0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.
Any other value: TEST TAP access will remain disabled out of power-up/system-reset.

12.2.1.17 CCFG_TAP_DAP_1 Register (Offset = 1FE8h) [Reset = FFC5C5C5h]

CCFG_TAP_DAP_1 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_TAP_DAP_1_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_TAP_DAP_1_TABLE.

Return to the Summary Table.

Test Access Points Enable 1

Figure 12-17 CCFG_TAP_DAP_1 Register
31302928272625242322212019181716
RESERVEDPBIST2_TAP_ENABLE
R-0hR-C5h
1514131211109876543210
PBIST1_TAP_ENABLEAON_TAP_ENABLE
R-C5hR-C5h
Table 12-19 CCFG_TAP_DAP_1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16PBIST2_TAP_ENABLERC5hEnable PBIST2 TAP.
0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.
Any other value: PBIST2 TAP access will remain disabled out of power-up/system-reset.
15-8PBIST1_TAP_ENABLERC5hEnable PBIST1 TAP.
0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.
Any other value: PBIST1 TAP access will remain disabled out of power-up/system-reset.
7-0AON_TAP_ENABLERC5hEnable AON TAP
0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.
Any other value: AON TAP access will remain disabled out of power-up/system-reset.

12.2.1.18 IMAGE_VALID_CONF Register (Offset = 1FECh) [Reset = FFFFFFFFh]

IMAGE_VALID_CONF is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_IMAGE_VALID_CONF_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_IMAGE_VALID_CONF_TABLE.

Return to the Summary Table.

Image Valid

Figure 12-18 IMAGE_VALID_CONF Register
313029282726252423222120191817161514131211109876543210
IMAGE_VALID
R-FFFFFFFFh
Table 12-20 IMAGE_VALID_CONF Register Field Descriptions
BitFieldTypeResetDescription
31-0IMAGE_VALIDRFFFFFFFFhThis field must have the address value of the start of the flash vector table in order to enable the boot FW in ROM to transfer control to a flash image.
Any illegal vector table start address value will force the boot FW in ROM to transfer control to the serial boot loader in ROM.

12.2.1.19 CCFG_PROT_31_0 Register (Offset = 1FF0h) [Reset = FFFFFFFFh]

CCFG_PROT_31_0 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_31_0_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_31_0_TABLE.

Return to the Summary Table.

Protect Sectors 0-31
Each bit write protects one 8KB flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect.

Figure 12-19 CCFG_PROT_31_0 Register
3130292827262524
WRT_PROT_SEC_31WRT_PROT_SEC_30WRT_PROT_SEC_29WRT_PROT_SEC_28WRT_PROT_SEC_27WRT_PROT_SEC_26WRT_PROT_SEC_25WRT_PROT_SEC_24
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
2322212019181716
WRT_PROT_SEC_23WRT_PROT_SEC_22WRT_PROT_SEC_21WRT_PROT_SEC_20WRT_PROT_SEC_19WRT_PROT_SEC_18WRT_PROT_SEC_17WRT_PROT_SEC_16
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
15141312111098
WRT_PROT_SEC_15WRT_PROT_SEC_14WRT_PROT_SEC_13WRT_PROT_SEC_12WRT_PROT_SEC_11WRT_PROT_SEC_10WRT_PROT_SEC_9WRT_PROT_SEC_8
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
76543210
WRT_PROT_SEC_7WRT_PROT_SEC_6WRT_PROT_SEC_5WRT_PROT_SEC_4WRT_PROT_SEC_3WRT_PROT_SEC_2WRT_PROT_SEC_1WRT_PROT_SEC_0
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
Table 12-21 CCFG_PROT_31_0 Register Field Descriptions
BitFieldTypeResetDescription
31WRT_PROT_SEC_31R1h0: Sector protected
30WRT_PROT_SEC_30R1h0: Sector protected
29WRT_PROT_SEC_29R1h0: Sector protected
28WRT_PROT_SEC_28R1h0: Sector protected
27WRT_PROT_SEC_27R1h0: Sector protected
26WRT_PROT_SEC_26R1h0: Sector protected
25WRT_PROT_SEC_25R1h0: Sector protected
24WRT_PROT_SEC_24R1h0: Sector protected
23WRT_PROT_SEC_23R1h0: Sector protected
22WRT_PROT_SEC_22R1h0: Sector protected
21WRT_PROT_SEC_21R1h0: Sector protected
20WRT_PROT_SEC_20R1h0: Sector protected
19WRT_PROT_SEC_19R1h0: Sector protected
18WRT_PROT_SEC_18R1h0: Sector protected
17WRT_PROT_SEC_17R1h0: Sector protected
16WRT_PROT_SEC_16R1h0: Sector protected
15WRT_PROT_SEC_15R1h0: Sector protected
14WRT_PROT_SEC_14R1h0: Sector protected
13WRT_PROT_SEC_13R1h0: Sector protected
12WRT_PROT_SEC_12R1h0: Sector protected
11WRT_PROT_SEC_11R1h0: Sector protected
10WRT_PROT_SEC_10R1h0: Sector protected
9WRT_PROT_SEC_9R1h0: Sector protected
8WRT_PROT_SEC_8R1h0: Sector protected
7WRT_PROT_SEC_7R1h0: Sector protected
6WRT_PROT_SEC_6R1h0: Sector protected
5WRT_PROT_SEC_5R1h0: Sector protected
4WRT_PROT_SEC_4R1h0: Sector protected
3WRT_PROT_SEC_3R1h0: Sector protected
2WRT_PROT_SEC_2R1h0: Sector protected
1WRT_PROT_SEC_1R1h0: Sector protected
0WRT_PROT_SEC_0R1h0: Sector protected

12.2.1.20 CCFG_PROT_63_32 Register (Offset = 1FF4h) [Reset = FFFFFFFFh]

CCFG_PROT_63_32 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_63_32_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_63_32_TABLE.

Return to the Summary Table.

Protect Sectors 32-63
Each bit write protects one 8KB flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect.

Figure 12-20 CCFG_PROT_63_32 Register
3130292827262524
WRT_PROT_SEC_63WRT_PROT_SEC_62WRT_PROT_SEC_61WRT_PROT_SEC_60WRT_PROT_SEC_59WRT_PROT_SEC_58WRT_PROT_SEC_57WRT_PROT_SEC_56
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
2322212019181716
WRT_PROT_SEC_55WRT_PROT_SEC_54WRT_PROT_SEC_53WRT_PROT_SEC_52WRT_PROT_SEC_51WRT_PROT_SEC_50WRT_PROT_SEC_49WRT_PROT_SEC_48
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
15141312111098
WRT_PROT_SEC_47WRT_PROT_SEC_46WRT_PROT_SEC_45WRT_PROT_SEC_44WRT_PROT_SEC_43WRT_PROT_SEC_42WRT_PROT_SEC_41WRT_PROT_SEC_40
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
76543210
WRT_PROT_SEC_39WRT_PROT_SEC_38WRT_PROT_SEC_37WRT_PROT_SEC_36WRT_PROT_SEC_35WRT_PROT_SEC_34WRT_PROT_SEC_33WRT_PROT_SEC_32
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
Table 12-22 CCFG_PROT_63_32 Register Field Descriptions
BitFieldTypeResetDescription
31WRT_PROT_SEC_63R1h0: Sector protected
30WRT_PROT_SEC_62R1h0: Sector protected
29WRT_PROT_SEC_61R1h0: Sector protected
28WRT_PROT_SEC_60R1h0: Sector protected
27WRT_PROT_SEC_59R1h0: Sector protected
26WRT_PROT_SEC_58R1h0: Sector protected
25WRT_PROT_SEC_57R1h0: Sector protected
24WRT_PROT_SEC_56R1h0: Sector protected
23WRT_PROT_SEC_55R1h0: Sector protected
22WRT_PROT_SEC_54R1h0: Sector protected
21WRT_PROT_SEC_53R1h0: Sector protected
20WRT_PROT_SEC_52R1h0: Sector protected
19WRT_PROT_SEC_51R1h0: Sector protected
18WRT_PROT_SEC_50R1h0: Sector protected
17WRT_PROT_SEC_49R1h0: Sector protected
16WRT_PROT_SEC_48R1h0: Sector protected
15WRT_PROT_SEC_47R1h0: Sector protected
14WRT_PROT_SEC_46R1h0: Sector protected
13WRT_PROT_SEC_45R1h0: Sector protected
12WRT_PROT_SEC_44R1h0: Sector protected
11WRT_PROT_SEC_43R1h0: Sector protected
10WRT_PROT_SEC_42R1h0: Sector protected
9WRT_PROT_SEC_41R1h0: Sector protected
8WRT_PROT_SEC_40R1h0: Sector protected
7WRT_PROT_SEC_39R1h0: Sector protected
6WRT_PROT_SEC_38R1h0: Sector protected
5WRT_PROT_SEC_37R1h0: Sector protected
4WRT_PROT_SEC_36R1h0: Sector protected
3WRT_PROT_SEC_35R1h0: Sector protected
2WRT_PROT_SEC_34R1h0: Sector protected
1WRT_PROT_SEC_33R1h0: Sector protected
0WRT_PROT_SEC_32R1h0: Sector protected

12.2.1.21 CCFG_PROT_95_64 Register (Offset = 1FF8h) [Reset = FFFFFFFFh]

CCFG_PROT_95_64 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_95_64_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_95_64_TABLE.

Return to the Summary Table.

Protect Sectors 64-95
Each bit write protects one flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect.

Figure 12-21 CCFG_PROT_95_64 Register
3130292827262524
WRT_PROT_SEC_95WRT_PROT_SEC_94WRT_PROT_SEC_93WRT_PROT_SEC_92WRT_PROT_SEC_91WRT_PROT_SEC_90WRT_PROT_SEC_89WRT_PROT_SEC_88
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
2322212019181716
WRT_PROT_SEC_87WRT_PROT_SEC_86WRT_PROT_SEC_85WRT_PROT_SEC_84WRT_PROT_SEC_83WRT_PROT_SEC_82WRT_PROT_SEC_81WRT_PROT_SEC_80
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
15141312111098
WRT_PROT_SEC_79WRT_PROT_SEC_78WRT_PROT_SEC_77WRT_PROT_SEC_76WRT_PROT_SEC_75WRT_PROT_SEC_74WRT_PROT_SEC_73WRT_PROT_SEC_72
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
76543210
WRT_PROT_SEC_71WRT_PROT_SEC_70WRT_PROT_SEC_69WRT_PROT_SEC_68WRT_PROT_SEC_67WRT_PROT_SEC_66WRT_PROT_SEC_65WRT_PROT_SEC_64
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
Table 12-23 CCFG_PROT_95_64 Register Field Descriptions
BitFieldTypeResetDescription
31WRT_PROT_SEC_95R1h0: Sector protected
30WRT_PROT_SEC_94R1h0: Sector protected
29WRT_PROT_SEC_93R1h0: Sector protected
28WRT_PROT_SEC_92R1h0: Sector protected
27WRT_PROT_SEC_91R1h0: Sector protected
26WRT_PROT_SEC_90R1h0: Sector protected
25WRT_PROT_SEC_89R1h0: Sector protected
24WRT_PROT_SEC_88R1h0: Sector protected
23WRT_PROT_SEC_87R1h0: Sector protected
22WRT_PROT_SEC_86R1h0: Sector protected
21WRT_PROT_SEC_85R1h0: Sector protected
20WRT_PROT_SEC_84R1h0: Sector protected
19WRT_PROT_SEC_83R1h0: Sector protected
18WRT_PROT_SEC_82R1h0: Sector protected
17WRT_PROT_SEC_81R1h0: Sector protected
16WRT_PROT_SEC_80R1h0: Sector protected
15WRT_PROT_SEC_79R1h0: Sector protected
14WRT_PROT_SEC_78R1h0: Sector protected
13WRT_PROT_SEC_77R1h0: Sector protected
12WRT_PROT_SEC_76R1h0: Sector protected
11WRT_PROT_SEC_75R1h0: Sector protected
10WRT_PROT_SEC_74R1h0: Sector protected
9WRT_PROT_SEC_73R1h0: Sector protected
8WRT_PROT_SEC_72R1h0: Sector protected
7WRT_PROT_SEC_71R1h0: Sector protected
6WRT_PROT_SEC_70R1h0: Sector protected
5WRT_PROT_SEC_69R1h0: Sector protected
4WRT_PROT_SEC_68R1h0: Sector protected
3WRT_PROT_SEC_67R1h0: Sector protected
2WRT_PROT_SEC_66R1h0: Sector protected
1WRT_PROT_SEC_65R1h0: Sector protected
0WRT_PROT_SEC_64R1h0: Sector protected

12.2.1.22 CCFG_PROT_127_96 Register (Offset = 1FFCh) [Reset = FFFFFFFFh]

CCFG_PROT_127_96 is shown in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_127_96_FIGURE and described in #CCFG_CCFG_MMAP1_CCFG_ALL_CCFG_PROT_127_96_TABLE.

Return to the Summary Table.

Protect Sectors 96-127
Each bit write protects one flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use.

Figure 12-22 CCFG_PROT_127_96 Register
3130292827262524
WRT_PROT_SEC_127WRT_PROT_SEC_126WRT_PROT_SEC_125WRT_PROT_SEC_124WRT_PROT_SEC_123WRT_PROT_SEC_122WRT_PROT_SEC_121WRT_PROT_SEC_120
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
2322212019181716
WRT_PROT_SEC_119WRT_PROT_SEC_118WRT_PROT_SEC_117WRT_PROT_SEC_116WRT_PROT_SEC_115WRT_PROT_SEC_114WRT_PROT_SEC_113WRT_PROT_SEC_112
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
15141312111098
WRT_PROT_SEC_111WRT_PROT_SEC_110WRT_PROT_SEC_109WRT_PROT_SEC_108WRT_PROT_SEC_107WRT_PROT_SEC_106WRT_PROT_SEC_105WRT_PROT_SEC_104
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
76543210
WRT_PROT_SEC_103WRT_PROT_SEC_102WRT_PROT_SEC_101WRT_PROT_SEC_100WRT_PROT_SEC_99WRT_PROT_SEC_98WRT_PROT_SEC_97WRT_PROT_SEC_96
R-1hR-1hR-1hR-1hR-1hR-1hR-1hR-1h
Table 12-24 CCFG_PROT_127_96 Register Field Descriptions
BitFieldTypeResetDescription
31WRT_PROT_SEC_127R1h0: Sector protected
30WRT_PROT_SEC_126R1h0: Sector protected
29WRT_PROT_SEC_125R1h0: Sector protected
28WRT_PROT_SEC_124R1h0: Sector protected
27WRT_PROT_SEC_123R1h0: Sector protected
26WRT_PROT_SEC_122R1h0: Sector protected
25WRT_PROT_SEC_121R1h0: Sector protected
24WRT_PROT_SEC_120R1h0: Sector protected
23WRT_PROT_SEC_119R1h0: Sector protected
22WRT_PROT_SEC_118R1h0: Sector protected
21WRT_PROT_SEC_117R1h0: Sector protected
20WRT_PROT_SEC_116R1h0: Sector protected
19WRT_PROT_SEC_115R1h0: Sector protected
18WRT_PROT_SEC_114R1h0: Sector protected
17WRT_PROT_SEC_113R1h0: Sector protected
16WRT_PROT_SEC_112R1h0: Sector protected
15WRT_PROT_SEC_111R1h0: Sector protected
14WRT_PROT_SEC_110R1h0: Sector protected
13WRT_PROT_SEC_109R1h0: Sector protected
12WRT_PROT_SEC_108R1h0: Sector protected
11WRT_PROT_SEC_107R1h0: Sector protected
10WRT_PROT_SEC_106R1h0: Sector protected
9WRT_PROT_SEC_105R1h0: Sector protected
8WRT_PROT_SEC_104R1h0: Sector protected
7WRT_PROT_SEC_103R1h0: Sector protected
6WRT_PROT_SEC_102R1h0: Sector protected
5WRT_PROT_SEC_101R1h0: Sector protected
4WRT_PROT_SEC_100R1h0: Sector protected
3WRT_PROT_SEC_99R1h0: Sector protected
2WRT_PROT_SEC_98R1h0: Sector protected
1WRT_PROT_SEC_97R1h0: Sector protected
0WRT_PROT_SEC_96R1h0: Sector protected