SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_TABLE_1 lists the memory-mapped registers for the WDT registers. All register offset addresses not listed in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_LEGEND shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
LOAD is shown in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_LOAD_FIGURE and described in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_LOAD_TABLE.
Return to the Summary Table.
Configuration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDTLOAD | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WDTLOAD | R/W | FFFFFFFFh | This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter is restarted to count down from the new value. If this register is loaded with 0x0000.0000, an interrupt is immediately generated. |
VALUE is shown in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_VALUE_FIGURE and described in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_VALUE_TABLE.
Return to the Summary Table.
Current Count Value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDTVALUE | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WDTVALUE | R | FFFFFFFFh | This register contains the current count value of the timer. |
CTL is shown in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_CTL_FIGURE and described in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_CTL_TABLE.
Return to the Summary Table.
Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTTYPE | RESEN | INTEN | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | INTTYPE | R/W | 0h | WDT Interrupt Type 0: WDT interrupt is a standard interrupt. 1: WDT interrupt is a non-maskable interrupt. 0h = Maskable interrupt 1h = Non-maskable interrupt |
1 | RESEN | R/W | 0h | WDT Reset Enable. Defines the function of the WDT
reset source (see PRCM:WARMRESET.WDT_STAT if enabled) 0: Disabled. 1: Enable the Watchdog reset output. 0h = Reset output Disabled 1h = Reset output Enabled |
0 | INTEN | R/W | 0h | WDT Interrupt Enable 0: Interrupt event disabled. 1: Interrupt event enabled. Once set, this bit can only be cleared by a hardware reset. 0h = Interrupt Disabled 1h = Interrupt Enabled |
ICR is shown in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_ICR_FIGURE and described in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_ICR_TABLE.
Return to the Summary Table.
Interrupt Clear
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDTICR | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WDTICR | W | 0h | This register is the interrupt clear register. A write of any value to this register clears the WDT interrupt and reloads the 32-bit counter from the LOAD register. |
RIS is shown in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_RIS_FIGURE and described in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_RIS_TABLE.
Return to the Summary Table.
Raw Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDTRIS | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | WDTRIS | R | 0h | This register is the raw interrupt status register.
WDT interrupt events can be monitored via this register if the
controller interrupt is masked. Value Description 0: The WDT has not timed out 1: A WDT time-out event has occurred |
MIS is shown in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_MIS_FIGURE and described in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_MIS_TABLE.
Return to the Summary Table.
Masked Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDTMIS | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | WDTMIS | R | 0h | This register is the masked interrupt status register.
The value of this register is the logical AND of the raw interrupt
bit and the WDT interrupt enable bit CTL.INTEN. Value Description 0: The WDT has not timed out or is masked. 1: An unmasked WDT time-out event has occurred. |
TEST is shown in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_TEST_FIGURE and described in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_TEST_TABLE.
Return to the Summary Table.
Test Mode
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | STALL | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TEST_EN | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | STALL | R/W | 0h | WDT Stall Enable 0: The WDT timer continues counting if the CPU is stopped with a debugger. 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the CPU is restarted, the WDT resumes counting. 0h = Disable STALL 1h = Enable STALL |
7-1 | RESERVED | R | 0h | Reserved |
0 | TEST_EN | R/W | 0h | The test enable bit 0: Enable external reset 1: Disables the generation of an external reset. Instead bit 1 of the INT_CAUS register is set and an interrupt is generated 0h = Test mode Disabled 1h = Test mode Enabled |
INT_CAUS is shown in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_INT_CAUS_FIGURE and described in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_INT_CAUS_TABLE.
Return to the Summary Table.
Interrupt Cause Test Mode
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CAUSE_RESET | CAUSE_INTR | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CAUSE_RESET | R | 0h | Indicates that the cause of an interrupt was a reset generated but blocked due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). |
0 | CAUSE_INTR | R | 0h | Replica of RIS.WDTRIS |
LOCK is shown in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_LOCK_FIGURE and described in #WDTIMERV2_0_NOSYNC_WRAPPER_WDTIMERV2_0_NOSYNC_WRAPPER_MAP1_WDTIMERV2_0_NOSYNC_WRAPPER_ALL_LOCK_TABLE.
Return to the Summary Table.
Lock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDTLOCK | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WDTLOCK | R/W | 0h | WDT Lock: A write of the value 0x1ACC.E551 unlocks the
watchdog registers for write access. A write of any other value
reapplies the lock, preventing any register updates (NOTE:
TEST.TEST_EN bit is not lockable). A read of this register returns the following values: 0x0000.0000: Unlocked 0x0000.0001: Locked |