SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The CC13x2x7 and CC26x2x7 device controller includes the Arm® NVIC. The NVIC and Arm® Cortex®-M4F prioritize and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The interrupt vector is fetched in parallel to state saving, thus enabling efficient interrupt entry. The processor supports tail-chaining, that is, back-to-back interrupts can be performed without the overhead of state saving and restoration. Software can set eight priority levels on seven exceptions (system handlers) and can set device interrupts.
Features of the NVIC are as follows: