SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Standard and fast modes are selected using a value in the I2C Master Timer Period I2C:MTPR register that results in an SCL frequency of 100 kbps for standard mode, or 400 kbps for fast mode.
The I2C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP where:
The I2C clock period is calculated as follows:
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP = 6
SCL_HP = 4
yields a SCL frequency of:
1 / SCL_PERIOD = 333 kHz
Table 24-1 lists examples of the timer periods used to generate both standard and fast-mode SCL frequencies, based on various system clock frequencies.
| System Clock (MHz) | Timer Period | Standard Mode (kpbs) | Timer Period | Fast Mode (kbps) |
|---|---|---|---|---|
| 4 | 0x01 | 100 | – | – |
| 8 | 0x03 | 100 | 0x01 | – |
| 16 | 0x07 | 100 | 0x01 | 400 |