SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The GPTM Synchronizer Control register (GPT:SYNC) in the GPTM0 block can be used to synchronize selected timers to begin counting at the same time. To do so, the timers must be started first. Setting a bit in the GPT:SYNC register causes the associated timer to perform the actions of a time-out event. An interrupt is not generated when the timers are synchronized. If a timer is being used in concatenated mode, only the bit for Timer A must be set in the GPT:SYNC register. The register description shows which timers can be synchronized.
Table 16-6 lists the actions for the time-out event performed when the timers are synchronized in the various timer modes.
| Mode | Count Direction | Time-Out Action |
|---|---|---|
| 16-bit and 32-bit one-shot (concatenated timers) | ─ | Not applicable |
| 16- bit and 32-bit periodic (concatenated timers) | Down | Count value = ILR |
| Up | Count value = 0 | |
| 16-bit and 32-bit one-shot (individual and split timers) | ─ | Not applicable |
| 16-bit and 32-bit periodic (individual and split timers) | Down | Count value = ILR |
| Up | Count value = 0 | |
| 16-bit and 32-bit edge-count (individual and split timers) | Down | Count value = ILR |
| Up | Count value = 0 | |
| 16-bit and 32-bit edge-time (individual and split timers) | Down | Count value = ILR |
| Up | Count value = 0 | |
| 16-bit PWM | Down | Count value = ILR |