SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Table 20-33 summarizes the event signals. For detailed event description, see the AUX_EVCTL:EVSTAT0 through AUX_EVCTL:EVSTAT3 registers in Section 20.8.3.
Index | Asynchronous Event Bus(1)(2) | Synchronous Event Bus(3)(4)(5) | ||
---|---|---|---|---|
Origin | Signal | SCE Rate | Bus Rate | |
[0:31] | DIO | AUXIO[0:31] | X | |
32 | AUX | MANUAL_EV | X | |
33 | System | AON_RTC_CH2 | X | |
34 | AON_RTC_CH2_DLY | X | ||
35 | AON_RTC_4KHZ | X | ||
36 | AON_BATMON_BAT_UPD | X | ||
37 | AON_BATMON_TEMP_UPD | X | ||
38 | SCLK_LF | X | ||
39 | PWR_DWN | X | ||
40 | MCU_ACTIVE | X | ||
41 | VDDR_RECHARGE | X | ||
42 | ACLK_REF | X | ||
43 | MCU_EV | X | ||
44 | MCU_OBSMUX0 | X | ||
45 | MCU_OBSMUX1 | X | ||
46 | AUX | AUX_COMPA | X | (X) |
47 | AUX_COMPB | X | (X) | |
48 | AUX_TIMER2_EV0 | X | (X) | |
49 | AUX_TIMER2_EV1 | X | (X) | |
50 | AUX_TIMER2_EV2 | X | (X) | |
51 | AUX_TIMER2_EV3 | X | (X) | |
52 | AUX_TIMER2_PULSE | X | (X) | |
53 | AUX | AUX_TIMER1_EV | X | (X) |
54 | AUX_TIMER0_EV | X | (X) | |
55 | AUX_TDC_DONE | X | ||
56 | AUX_ISRC_RESET_N | X | ||
57 | AUX_ADC_DONE | X | ||
58 | AUX_ADC_IRQ | X | ||
59 | AUX_ADC_FIFO_ALMOST_FULL | X | ||
60 | AUX_ADC_FIFO_NOT_EMPTY | X | ||
61 | AUX_SMPH_AUTOTAKE_DONE | X | ||
62 | DAC_HOLD_ACTIVE | X | (X) | |
63 | TIMER2_CLKSWITCH_RDY | X |
The update rate is determined by either event synchronization or the operational rate of the synchronous peripheral that generates it.
Table 20-33 shows the following:
This configurability serves resource sharing between the System CPU and the Sensor Controller.
Because of synchronization there will always be a time delay between the asynchronous and the synchronous version of an event of asynchronous origin. The System CPU may require minimum synchronization latency, in which case the synchronization must happen at bus clock rate. A slow AUX SCE clock rate will then not affect the latency. On the other hand, when the SCE clock rate is less than the bus clock rate, any event synchronized at the bus clock rate will experience lower latency when the MCU domain is active. This may not be desirable for a Sensor Controller task or for Timer01. In this case, the event synchronization rate must equal SCE clock rate.